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[Other resource] filter-vhdl-code DL : 0: filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.
Update : 2008-10-13 Size : 169.68kb Publisher : petri
[VHDL-FPGA-Verilog] fifo的vhdl原代码 DL : 0: 本文为verilog的源代码-In this paper, the source code for Verilog
Update : 2025-02-17 Size : 22kb Publisher : 艾霞
[VHDL-FPGA-Verilog] 一篇用VHDL实现快速傅立叶变换的论文 DL : 0: 一篇用VHDL实现快速傅立叶变换的论文，包括原理分析和代码实现，印度圣雄甘地大学M.A.学院提供-VHDL with a Fast Fourier Transform papers, including the principle of analysis and implementation of the code, the Mahatma Gandhi Institute of the University of Marat
Update : 2025-02-17 Size : 61kb Publisher :
[VHDL-FPGA-Verilog] VHDL实例 DL : 0: 各种常用模块的VHDL描叙实例，PDF格式-various modules used VHDL depicts examples, PDF format
Update : 2025-02-17 Size : 165kb Publisher : 付杰
[VHDL-FPGA-Verilog] FFT的VHDL源代码 DL : 0: FFT的VHDL源代码-fft vhdl source code
Update : 2025-02-17 Size : 29kb Publisher : 阿林
[VHDL-FPGA-Verilog] FFT变换的IP核的源代码 VHDL~ DL : 0: FFT变换的IP核的源代码 VHDL~-FFT IP core of the source code for VHDL ~
Update : 2025-02-17 Size : 31kb Publisher : 陈旭
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] pci 的vhdl 源代码 DL : 0: pci 的vhdl 源代码-The source code of PCI VHDL.
Update : 2025-02-17 Size : 3kb Publisher : 陈旭
[VHDL-FPGA-Verilog] MPSK调制与解调VHDL程序与仿真 DL : 0: MPSK调制与解调VHDL程序与仿真,具有很高的参考价值!!vhdl代码!-MPSK modulation and demodulation process and VHDL simulation, high reference value! ! VHDL code!
Update : 2025-02-17 Size : 78kb Publisher : 温暖感
[Software Engineering] filter-vhdl-code DL : 0: filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.-filter-vhdl-code.rar for the integrity of filter VHDL procedures, can be used for IIR and FIR filters realize simulation and verification, including an integrated code. Use version ISE6.3.
Update : 2025-02-17 Size : 169kb Publisher : petri
[VHDL-FPGA-Verilog] AMBAcode(vhdl) DL : 0: vhdl实现的amba代码-realize the AMBA VHDL code
Update : 2025-02-17 Size : 197kb Publisher : sk
[VHDL-FPGA-Verilog] vhdl DL : 0: 《数字信号处理的FPGA实现》（第二版）光盘VHDL代码-" The FPGA digital signal processing to achieve" (second edition) CD-ROM VHDL code
Update : 2025-02-17 Size : 246kb Publisher : 王昊
[VHDL-FPGA-Verilog] interleaver-vhdl DL : 0: VHDL编写的基于FPGA的4-8交织器代码，有需要的下来-4-8 prepared VHDL code interleaver
Update : 2025-02-17 Size : 1kb Publisher : cab
[VHDL-FPGA-Verilog] CLA.VHDL.CODE DL : 0: cla vhdl code with a picture files.
Update : 2025-02-17 Size : 332kb Publisher : YD
[VHDL-FPGA-Verilog] fir-vhdl-code DL : 0: FIR FILTER CODE with VHDL
Update : 2025-02-17 Size : 112kb Publisher : mahmoud
[Books] VHDL DL : 1: A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation. -A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation.
Update : 2025-02-17 Size : 7kb Publisher : Michael Lee
[VHDL-FPGA-Verilog] DWT-VHDL DL : 0: 小波变换的VHDL代码，内带正变换逆变换的测试文件。-Wavelet transform VHDL code, with a positive transformation within the inverse transform of the test file.
Update : 2025-02-17 Size : 18kb Publisher : Janee
[VHDL-FPGA-Verilog] mdf-code-4m-net DL : 0: median filter algorithm , VHDL code
Update : 2025-02-17 Size : 20kb Publisher : ravitikkam
[VHDL-FPGA-Verilog] VHDL DL : 0: VHDL code for QAM modulation
Update : 2025-02-17 Size : 9kb Publisher : Pratik
[VHDL-FPGA-Verilog] Digital-FM-transmitter-VHDL-coding DL : 0: it is VHDL code for Digital fm modem transmitter block.
Update : 2025-02-17 Size : 10kb Publisher : anbu

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