Search - VHDL Code of dct

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[VHDL-FPGA-Verilog] dct

Description: 离散余弦变换的verilog源代码，经过验证可实现-Discrete cosine transform of Verilog source code can be verified
Platform: | Size: 27648 | Author: 罗伟 | Hits:

Description: 这个DCT的源代码Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA-The DCT of source code Core was tested on Digilent S3 board with Spartan Xc3S1000 FPGA
Platform: | Size: 51200 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] 8x8DCT

Description: 8x8DCT verilog code 一次輸入8個點-8x8DCT verilog code once the importation of eight points
Platform: | Size: 8416256 | Author: Emuil | Hits:

[VHDL-FPGA-Verilog] 8x8IDCT

Description: 8x8 iDCT verilog code 一次輸入八個點-8x8 iDCT verilog code once the importation of eight points
Platform: | Size: 8303616 | Author: Emuil | Hits:

[Graph program] szsy

Description: dct实现数字水印的源代码内附说明 matlab实现-DCT digital watermark containing a description of the source code matlab realize
Platform: | Size: 759808 | Author: xdmgw | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Platform: | Size: 29696 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] dct-code

Description: 离散余弦变换的VHDL实现，不错的代码和方法-Discrete cosine transform VHDL realization of good code and methods
Platform: | Size: 30720 | Author: 宋雪兵 | Hits:

[VHDL-FPGA-Verilog] 1DCT_VHDL

Description: VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.
Platform: | Size: 11264 | Author: NULL | Hits:

[source in ebook] 63535312DCTofJPEG

Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Platform: | Size: 2048 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] Chapter6-9

Description: 第六章到第九章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter VI to Chapter IX of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 6281216 | Author: xiao | Hits:

[mpeg mp3] mpeg2_idct_hw

Description: 2-D的DCT/IDCT在軟硬體上的verilog code-dct/idct source code for soc
Platform: | Size: 10801152 | Author: 陳伯綸 | Hits:

[VHDL-FPGA-Verilog] dct

Description: 离散余弦变换的设计源代码以及测试源代码和仿真图-Design of discrete cosine transform source code and test source code and simulation plan
Platform: | Size: 342016 | Author: cong | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: verilog code for DCT and IDCT (JPEG)
Platform: | Size: 63488 | Author: Dang Tien Dat | Hits:

[VHDL-FPGA-Verilog] DCT2

Description: 2 维 DCT的VHDL实现以及测试代码， -2-D DCT of the VHDL implementation and test code
Platform: | Size: 6144 | Author: li | Hits:

[VHDL-FPGA-Verilog] DCT

Description: Discrete Cosine transform VHDL code, with a positive transformation within the inverse transform of the test file.
Platform: | Size: 32768 | Author: hoon | Hits:

[VHDL-FPGA-Verilog] wallace

Description: wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of both dct and dwrt applications-wallacw tree multiplier code in vhdl language mainy used for the multiplications in the image [processing of both dct and dwrt applications
Platform: | Size: 3072 | Author: ganesh | Hits:

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[VHDL-FPGA-Verilog] DCT

[VHDL-FPGA-Verilog] dct

[Graph program] quantizer

[VHDL-FPGA-Verilog] 8x8DCT

[VHDL-FPGA-Verilog] 8x8IDCT

[Graph program] szsy

[VHDL-FPGA-Verilog] DCT_IDCT

[VHDL-FPGA-Verilog] dct-code

[VHDL-FPGA-Verilog] 1DCT_VHDL

[source in ebook] 63535312DCTofJPEG

[VHDL-FPGA-Verilog] Chapter6-9

[mpeg mp3] mpeg2_idct_hw

[VHDL-FPGA-Verilog] dct

[VHDL-FPGA-Verilog] DCT_IDCT

[VHDL-FPGA-Verilog] DCT2

[VHDL-FPGA-Verilog] DCT

[VHDL-FPGA-Verilog] wallace

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