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[Other resource] simplevhdl

Description: 我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3 -8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master
Platform: | Size: 4034 | Author: yvonne | Hits:

[Embeded-SCM Develop] 卷积码、CRC

Description: 卷积码的C源程序，包括编码器和译码器。 还有一个是循环荣誉校验的vhdl]源码。-convolution of C source code, including the encoder and decoder. There is a cycle of the calibration honor VHDL] source.
Platform: | Size: 6144 | Author: 潘华林 | Hits:

[VHDL-FPGA-Verilog] simplevhdl

Description: 我是VHDL的初学者，这是我自己编译的简单的几个VHDL码，功能有3-8解码器及其testbench,16位寄存器及其testbench和交通灯。 希望能和其他初学者一起讨论学习，并得到高手的指点-I VHDL beginners, this is my own translation of a few simple VHDL code. 3-8 function decoder and testbench, 16 Register and testbench and traffic lights. Hopes to be able to discuss other beginners learning, and with the guidance of the master
Platform: | Size: 4096 | Author: yvonne | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[VHDL-FPGA-Verilog] dec.vhd

Description: vhdl code for a 16 bit decoder design
Platform: | Size: 2048 | Author: siluyuan | Hits:

[VHDL-FPGA-Verilog] vhdltest

Description: 自己设计的几个VHDL程序，包括译码器电路，多路开关，比较器应用，和16乘8RAM电路，各模块及最终的顶层原理图和引脚我都已给好，希望对大家的学习有所帮助-A few of their own design VHDL procedures, including the decoder circuit, multiple switches, comparator applications, and 16 by 8RAM circuit, each module and final top-level schematic and pins I have been to the good hope of learning to everyone help
Platform: | Size: 910336 | Author: 李晓 | Hits:

[ELanguage] 16b20b_Decoder

Description: VHDL实现的16B/20B解码器。包含两个8B/10B解码器。采用级联方式实现-VHDL implementation 16B/20B decoder. Contains two 8B/10B decoder. Be achieved by cascading
Platform: | Size: 31744 | Author: Kevin | Hits:

[VHDL-FPGA-Verilog] 4-16.doc

Description: 4-16译码器，用VHDL编写的，可以直接下载到可编程逻辑器件中-4-16 decoder, written with VHDL, can be directly downloaded to the programmable logic device
Platform: | Size: 3072 | Author: bbdbdb | Hits:

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