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[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[VHDL-FPGA-Verilog] cf_dpsk

Description:
Platform: | Size: 745472 | Author: 周 | Hits:

[Modem program] all_digital_fm_receiver_latest

Description: Fm receiver using DP-Fm receiver using DPLL
Platform: | Size: 112640 | Author: sai | Hits:

[VHDL-FPGA-Verilog] DP

Description: TIC6000系列 C67浮点DSP处理器 派发站源代码-TIC6000 floating-point DSP processor series C67 station source code distributed
Platform: | Size: 18432 | Author: 杨惠 | Hits:

[Software Engineering] chuzuche

Description: 一款基于VHDL的EDA计程车计费系统的设计.熟悉Quartus2操作环境-LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL USE IEEE.STD_LOGIC_UNSIGNED.ALL ENTITY liuxuanyi IS PORT(C:IN STD_LOGIC_VECTOR(2 DOWNTO 0) DP: OUT STD_LOGIC A1,A2,A3,B1,B2,B3:IN STD_LOGIC_VECTOR(3 DOWNTO 0) D:OUT STD_LOGIC_VECTOR(3 DOWNTO 0))
Platform: | Size: 72704 | Author: 邱壮雄 | Hits:

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