Search - VHDL LCD VHDL

Search - VHDL LCD VHDL - List

[Other] VHDL LCD 控制模块 VHDL 代码 DL : 1: VHDL LCD 控制模块 VHDL 代码，金一倍EDA2000试验箱试验七VHDL源
Update : 2009-07-29 Size : 601.69kb Publisher : laobi1
[uCOS] Exp2-Lcd DL : 0: ARM7 不带操作系统的LCD实验原代码-ARM7 without LCD experimental operating system source code
Update : 2025-02-17 Size : 839kb Publisher : 阿邱
[VHDL-FPGA-Verilog] LCD显示实验 DL : 0: ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
Update : 2025-02-17 Size : 35kb Publisher : xf
[Program doc] 用VHDL语言在CPLD_FPGA上实现浮点运算 DL : 0: 用VHDL语言在CPLD/FPGA上实现浮点运算的方法-in VHDL CPLD/FPGA achieve floating-point computation methods
Update : 2025-02-17 Size : 81kb Publisher : wei
[VHDL-FPGA-Verilog] lcdexample DL : 0: cpld实现与液晶屏并口通信，VHDL 语言编程。对VHDL初学者应该有帮助的。-cpld achieve parallel with the LCD screen communications, VHDL programming. Right VHDL beginners should help.
Update : 2025-02-17 Size : 1kb Publisher : 黄小光
[source in ebook] some-usful-vhdl-source-code DL : 0: 一些实用的VHDL源码，有各种信号调制的，还有LCD控制的，出租车计价器等等源码。-some practical VHDL source code, a variety of signal modulation, there is the LCD control. taximeters, etc. source.
Update : 2025-02-17 Size : 1.22mb Publisher : 雨风
[VHDL-FPGA-Verilog] DJDPLJ_T DL : 0: 本VHDL源代码由顶层模块、测频模块、驱动模块、计算模块、LCD显示模块、复位模块组成，能精确检测从1--100M频率，误差极小且恒定。-the VHDL source code from the top module, measuring frequency module, driver modules, modules, LCD display module, reduction modules, can be used to accurately detect from 1-- 100M frequency, constant and very small errors.
Update : 2025-02-17 Size : 470kb Publisher : 刘刚
[VHDL-FPGA-Verilog] LCD DL : 0: vhdl经典源代码——LCD控制，入门者必须掌握-vhdl classical source code-- LCD control, beginners must master
Update : 2025-02-17 Size : 250kb Publisher : jeffery
[VHDL-FPGA-Verilog] lcd DL : 0: 用FPGA来控制2*16LCD的程序，采用VHDL语言来编写，并且我把他转换为verilog语言，有意者请联系；
Update : 2025-02-17 Size : 1kb Publisher : 赵雯
[VHDL-FPGA-Verilog] lcd DL : 0: VHDL接口电路实用源程序，这个是LCD液晶显示器的。-VHDL source utility interface circuit, this is the LCD liquid crystal display.
Update : 2025-02-17 Size : 1.11mb Publisher : gjd
[SCM] LCD DL : 0: 单片机驱动LCD液晶字符显示的驱动程序用VHDL语言编写-Single-chip LCD driver liquid crystal display driver of characters using VHDL language
Update : 2025-02-17 Size : 1kb Publisher : dakai
[VHDL-FPGA-Verilog] LCD DL : 0: 基于vhdl语言的LCD控制程序代码及仿真-Based on the VHDL language LCD control and simulation code
Update : 2025-02-17 Size : 5kb Publisher : hlj1232123
[VHDL-FPGA-Verilog] lcd DL : 0: 利用VHDL语言编写,在lcd上显示计数.-Using VHDL language, in the lcd display count.
Update : 2025-02-17 Size : 3kb Publisher : mao
[VHDL-FPGA-Verilog] sram+lcd DL : 0: 用vhdl格式写的sram源代码，把扩展名txt改为.v即可-VHDL format used to write the SRAM source code, to be re-txt extension. V can
Update : 2025-02-17 Size : 2kb Publisher : 郭艳红
[Wavelet] singt DL : 0: 实现了方波、正弦波、三角波的输出，同时在LCD模块中用状态机的方法实现LCD的对应显示：当输出正弦波，LCD显示“SIN”；当输出方波，LCD显示“REC”；当输出三角波，显示“TRI”；复位和其它位置波形显示“UNI”。-Realize a square wave, sine wave, triangle wave output, while in the LCD module using the state machine approach to achieve the corresponding LCD display: When the output sine wave, LCD display
Update : 2025-02-17 Size : 1.01mb Publisher : Emma
[VHDL-FPGA-Verilog] 45561564 DL : 0: 典型实例10.8 字符LCD接口的设计与实现软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects \ project folder inside 3. the distribution of the source file and pin in \ rtl folder inside 4. download files in \ download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
Update : 2025-02-17 Size : 306kb Publisher : 王磊
[VHDL-FPGA-Verilog] LCD DL : 0: lcd verilog hdl 源码可以直接使用，适用modelsim-lcd verilog HDL source
Update : 2025-02-17 Size : 195kb Publisher : xiedongliang
[VHDL-FPGA-Verilog] DE2LCD_(VHDL) DL : 0: DE2控制LCD显示(VHDL编写对LCD的控制)-DE2 LCD
Update : 2025-02-17 Size : 5kb Publisher : no4
[VHDL-FPGA-Verilog] LCD DL : 0: LCD 16x2 Driver with UCF static text
Update : 2025-02-17 Size : 1.29mb Publisher : linchkid
[VHDL-FPGA-Verilog] lcd DL : 0: lcd controler by vhdl
Update : 2025-02-17 Size : 2.64mb Publisher : abdallahreda

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