Search - VHDL LMS

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[Other resource] FPGA_LMS DL : 1: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Update : 2008-10-13 Size : 264.75kb Publisher : 黄鹤
[VHDL-FPGA-Verilog] FPGA_LMS DL : 1: VHDL写的LMS算法程序。利用本地正弦信号，根据LMS算法对输入信号进行跟踪。用以产生和输入信号同频同相的本地信号。-VHDL LMS algorithm written procedures. The use of local sinusoidal signal, according to the LMS algorithm for tracking the input signal. Used to produce and the input signal with frequency phase with the local signal.
Update : 2025-02-17 Size : 264kb Publisher : 黄鹤
[Other] zishiyinglvbodebiyesheji DL : 0: 论文针对数字通信系统中，由于码间串扰(ISI)和信道加性噪声的干扰，导致信号在接收端产生误码，设计了基于LMS算法的自适应均衡器(滤波器)，并通过硬件描述语言VHDL和现场可编程逻辑器件FPGA实现均衡器的硬件实现。是一篇标准的毕业论文,有需要的朋友可以拿来做参考-Thesis for digital communications systems, crosstalk due to inter-symbol (ISI) and additive noise channel interference, leading to signals generated in the receiver error, design algorithm based on LMS adaptive equalizer (filter), and through hardware description languages VHDL and Field Programmable Logic Device FPGA hardware equalizer realize realize. Is a standard thesis, there is a need to make friends can be used as reference
Update : 2025-02-17 Size : 2.24mb Publisher : YZ
[VHDL-FPGA-Verilog] fir6dlms DL : 1: lms的verilog代码，我找了好久在才找的的，好东西，大家一起学习-LMS of the Verilog code, I am looking for a long time before looking at the good things we can work together to learn
Update : 2025-02-17 Size : 1kb Publisher : 李允
[VHDL-FPGA-Verilog] ante DL : 0: 智能天线自适应LMS算法，假设具有4个天线阵元。-Smart antenna adaptive LMS algorithm, the assumption that with four million antenna array.
Update : 2025-02-17 Size : 4kb Publisher : 黄虎
[source in ebook] LMS_FIR DL : 0: 一种LMS数字自适应滤波器的硬件实现方法，用VHDL设计文件。-LMS adaptive filter of a digital hardware implementation methods, VHDL design files.
Update : 2025-02-17 Size : 245kb Publisher :
[matlab] equizer DL : 0: HART协议的均衡器设计 DCT LMS 设计 + 位同步设计，仿真证明了设计的有效性-HART protocol design DCT LMS equalizer design+ Bit synchronous design, simulation proves the validity of the design
Update : 2025-02-17 Size : 21kb Publisher : 进正化
[VHDL-FPGA-Verilog] adaptive_lms_equalizer_latest.tar DL : 0: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random. To handle this, multipath affected channels require Equalizers at receaver end. such equalizer uses different learning Algorithms for identifying channels continuously. This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic.
Update : 2025-02-17 Size : 14kb Publisher : Arun
[VHDL-FPGA-Verilog] AdaptiveLMSequalizer DL : 0: 通信中的用的LMS均衡算法VHDL实现，代码不长，很容易看懂-Communication with the LMS equalization algorithm to achieve VHDL code is not long, it is easy to understand
Update : 2025-02-17 Size : 3kb Publisher : 王王
[VHDL-FPGA-Verilog] lms DL : 0: 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
Update : 2025-02-17 Size : 1kb Publisher : onion
[VHDL-FPGA-Verilog] LMS_ DL : 0: Implement LMS vhdl code.
Update : 2025-02-17 Size : 1kb Publisher : Hem
[VHDL-FPGA-Verilog] LMS_filter DL : 0: verilog HDL 写的LMS滤波器-LMS filter using verilog HDL language
Update : 2025-02-17 Size : 342kb Publisher : rayax
[Embeded-SCM Develop] LMS DL : 0: 布斯算法 LMS算法布斯算法 LMS算法布斯算法 LMS算法-Booth algorithm LMS algorithm LMS operator operator Fabu Si Fa Busi algorithm LMS algorithm LMS algorithm Operator Fa Busi
Update : 2025-02-17 Size : 45kb Publisher : 龙崎
[VHDL-FPGA-Verilog] fir_lms DL : 0: 基于FIR滤波器的自适用滤波器的实现 vhDL语言-FIR LMS
Update : 2025-02-17 Size : 1kb Publisher : hejianhua
[VHDL-FPGA-Verilog] fir6dlms DL : 0: lms算法，自适应滤波器中使用fir滤波器对信号的码间干扰进行均衡-lms
Update : 2025-02-17 Size : 1kb Publisher : lvchangbo
[VHDL-FPGA-Verilog] ERROR_COUNTING_BLOCK DL : 0: vhdl code for error counting blk in lms algorithm
Update : 2025-02-17 Size : 5kb Publisher : lekshmi
[VHDL-FPGA-Verilog] trunk DL : 0: code for adaptive lms equilizer
Update : 2025-02-17 Size : 29kb Publisher : subha
[VHDL-FPGA-Verilog] LMS-vhdl-coad- DL : 0: 基于quartus的LMS 自适应滤波器代码，适合初学者 -The LMS adaptive filter based on quartus code, suitable for beginners
Update : 2025-02-17 Size : 15kb Publisher : jialiangquan
[Other] Quartus-VHDL-lms DL : 0: 使用VHDL语言在quartusII中实现自适应滤波算法-The filtering algorithm
Update : 2025-02-17 Size : 17kb Publisher : leon
[Other] vhdl-lms DL : 0: The program using the MATLAB simulation and VHDL implementation of LMS adaptive filter, filter the 50Hz sinusoidal frequency noise
Update : 2025-02-17 Size : 18kb Publisher : li

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