Search - VHDL LTE

Search - VHDL LTE - List

[Communication] Turbo DL : 1: 利用3GPP交织器和LTE交织器完成turbo码的仿真并做比较，不同解码算法的比较-Using 3GPP Interleaver and complete LTE interleaver turbo code simulation and comparison, a comparison of different decoding algorithms
Update : 2025-02-17 Size : 110kb Publisher : 老五
[Software Engineering] 3GPP DL : 0: Update : 2025-02-17 Size : 43kb Publisher : hamza
[VHDL-FPGA-Verilog] 10.1.1.88.7680 DL : 0: ofdm in vhdl for lte
Update : 2025-02-17 Size : 637kb Publisher : jim
[VHDL-FPGA-Verilog] lte_fft_xmp125 DL : 0: vhdl for ofdm lte application
Update : 2025-02-17 Size : 66kb Publisher : ingo
[VHDL-FPGA-Verilog] 6soft_247MHz_channel DL : 0: lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟 input_buffer.vhd 输入控制 ri_addr_gen.vhd ri信息提取 ul_common_pack.vhd 变量定义 write_ram.vhd 解交织 deintlv_data.txt 数据源 deintlv_data_ack.txt ack信息源 deintlv_data_cqi.txt cqi信息源 deintlv_data_ri.txt ri信息源 sim_lib.tcl altera库编译 ue.tcl modelsim 脚本-upstream channel deinterleaving lte demultiplexing: RTL: ack_addr_gen.vhd ack address generation data_addr_gen.vhd data address generation control unit de_interl_mux_con_top.vhd de_interl_mux_con_ctrl.vhd top de_interl_mux_con_tt.vhd test platform de_mux_ram.vhd ram deinterl_pack.vhd delay variable definition delay.vhd delayb.vhd delay input_buffer.vhd input control information extraction ul_common_pack.vhd ri_addr_gen.vhd ri definition of a variable data source write_ram.vhd deinterleaving deintlv_data.txt deintlv_data_cqi.txt cqi deintlv_data_ack.txt ack information source information sources sources of information deintlv_data_ri.txt ri sim_lib. tcl altera library compile script ue.tcl modelsim
Update : 2025-02-17 Size : 196kb Publisher : renliang
[VHDL-FPGA-Verilog] Gerhard-Fettweis-at-BWRC-2009-09-18 DL : 0: Signal processing and its implementation for LTE-Advanced
Update : 2025-02-17 Size : 7.92mb Publisher : saravanan
[VHDL-FPGA-Verilog] VHDL-codes DL : 0: important codes used in LTE physical layer
Update : 2025-02-17 Size : 598kb Publisher : motaz
[Program doc] interleaver-vhdl-code DL : 0: lte turbo interleaver
Update : 2025-02-17 Size : 140kb Publisher : sampath
[VHDL-FPGA-Verilog] CRC DL : 0: 4G-LTE标准中turbo编码所用到的CRC编码，绝对可用！(CRC encoding turbo encoding used in 4G-LTE standard)
Update : 2025-02-17 Size : 2kb Publisher : 江41543434