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[VHDL-FPGA-Verilog100个vhdl设计例子

Description: 内附多路选择器,74系列芯片VHDL源码,加法器,FIR,比较器等大量例子,对初学VHDL语言很有好处。可用maxplus,quartus,synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233472 | Author: 杰轩 | Hits:

[VHDL-FPGA-Verilogfifo数据缓冲器的vhdl源程序

Description: 编了个8*8位的fifo数据缓冲器的vhdl源程序,是经过quartusII4.2编译成功的程序。。希望能跟各位交流-Bianlegan 8* 8 of the data buffer fifo VHDL source, after quartusII4.2 compiler successful procedures. . Hope you enjoy the exchanges
Platform: | Size: 1024 | Author: 夏社 | Hits:

[VHDL-FPGA-Verilogquartus II中文用户教程(英文版的完全翻译)

Description: quartus II中文用户教程(英文版的完全翻译),和一切爱好可编程器件的同仁共勉之-Quartus II Chinese user guide (English version of the full translation) love and all programmable devices colleagues share Zhi
Platform: | Size: 844800 | Author: 田晶昌 | Hits:

[VHDL-FPGA-VerilogVHDL-Clock

Description: 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.
Platform: | Size: 4096 | Author: 单单 | Hits:

[VHDL-FPGA-VerilogVHDL_Memory_Library_Code

Description: 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
Platform: | Size: 23552 | Author: Jawen | Hits:

[VHDL-FPGA-VerilogVHDL-six

Description: 用VHDL语言实现六分频,并且已经通过编译和仿真。由此可举一反三,实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
Platform: | Size: 25600 | Author: philohb | Hits:

[Crack Hack3des-VHDL

Description: 3des的VHDL实现,适用于quartus环境-3des VHDL applicable to the environment quartus
Platform: | Size: 95232 | Author: xin | Hits:

[VHDL-FPGA-Verilogbox

Description: 用vhdl语言编写的基于fpga的波形发生器,使用了quartusII程序。可以在1602液晶显示器上显示目前的波形种类。产生的波形分别是正弦波,三角波,锯齿波和方波。-VHDL language using FPGA-based waveform generator, using the procedures quartusII. 1602 liquid crystal display can show the current waveform types. Generated waveforms are sine wave, triangle wave, sawtooth and square wave.
Platform: | Size: 1708032 | Author: zhg | Hits:

[assembly languageSAA7113

Description: 用quartusII编写的,基于vhdl语言的按键加法器,从0到11,也可通过拨码开关控制,从11到0,加入了键盘防手抖。-
Platform: | Size: 1633280 | Author: yl | Hits:

[VHDL-FPGA-VerilogFT245_R_W

Description: USB芯片FT245BM读写代码,在Quartus II V7.2上测试成功!---Verilog语言.
Platform: | Size: 1644544 | Author: | Hits:

[VHDL-FPGA-Verilog8b_10b

Description: vhdl编写,8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: | Size: 72704 | Author: 聂样 | Hits:

[VHDL-FPGA-Veriloguart

Description: VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
Platform: | Size: 212992 | Author: 朱兆斌 | Hits:

[VHDL-FPGA-Verilogfftvhdl

Description: 用VHDL语言实现的FFT源代码,好使的程序,大家试试。QUARTUS II软件开发-VHDL language used to achieve the FFT source code, so that the procedure, we try. QUARTUS II software development
Platform: | Size: 28672 | Author: 王真 | Hits:

[VHDL-FPGA-Verilogvhdl

Description: VHDL教程 ppt版 绪论 第一章 VHDL基本结构 第二章 VHDL语言元素 第三章 VHDL的描述风格 第四章 VHDL的主要描述语句 第五章 组合逻辑电路设计 第六章 时序逻辑电路设计-Ppt version of VHDL Tutorial VHDL Introduction Chapter I Chapter II the basic structure of VHDL language element of VHDL in Chapter III Chapter IV describes the style of the main description language VHDL Chapter V combinational logic circuit design of Chapter VI of sequential logic circuit design
Platform: | Size: 1081344 | Author: 陈松 | Hits:

[OtherquartusII

Description: 华为公司内部quartus教程。quartus工具使用详细说明。-Huawei internal Quartus Tutorial. Quartus tool in detail.
Platform: | Size: 2458624 | Author: 王伟 | Hits:

[VHDL-FPGA-Verilogdds

Description: 直接数字频率合成器,基于vhdl语言,在qartus II上实现,下载调试成功-Direct digital frequency synthesizer, based on the VHDL language, in qartus II achieved a successful download debugging
Platform: | Size: 316416 | Author: 浮云 | Hits:

[VHDL-FPGA-Verilog100vhdl

Description: 100个简单而使用的以 Quartus软件为基础的 VHDL程序 看看对你会有一定的帮助-100 simple and used to Quartus software VHDL-based procedures to see if you will help
Platform: | Size: 235520 | Author: 时亮亮 | Hits:

[VHDL-FPGA-VerilogPLL

Description: PLL 时钟模块  Quartus II平台的简单设计实例 附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Platform: | Size: 806912 | Author: 许东滨 | Hits:

[VHDL-FPGA-VerilogUART-VHDL-QUARTUS

Description: uart vhdl quartus for altera
Platform: | Size: 212992 | Author: gilang | Hits:

[VHDL-FPGA-Verilogtraffic-light-vhdl-Quartus-II6.0

Description: 简单的交通灯vhdl程序 Quartus II6.0下的程序 包含图形仿真-easy traffic light vhdl Quartus II6.0
Platform: | Size: 207872 | Author: 睿宸 | Hits:
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