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Description: 步进电机控制，控制器,控制电机的VHDL源程序,,多平台
Digital_030423.rar - 服务器的的板在载控制器的AHDL程序,包括原理图编译,用-stepper motor control, controllers, motor control VHDL source files, and Multi-platform Digital_030423.rar-server contains the controller board in the tap procedure , including diagram compiler, and
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Size: 17849 |
Author: nmghjmhgj |
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Description: 步进电机控制，控制器,控制电机的VHDL源程序,,多平台
Digital_030423.rar - 服务器的的板在载控制器的AHDL程序,包括原理图编译,用-stepper motor control, controllers, motor control VHDL source files, and Multi-platform Digital_030423.rar-server contains the controller board in the tap procedure , including diagram compiler, and
Platform: |
Size: 17408 |
Author: |
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Description: UIP完整的协议栈，可以应用于8位或16位单片机作web-server功能，该协议栈的一个显著的优点就是需要的空间极小。-UIP complete protocol stack, can be applied to 8-bit or 16-bit single-chip microcomputer for the web-server functionality, the protocol stack, a significant advantage is that a very small space requirements.
Platform: |
Size: 2199552 |
Author: 张勃 |
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Description: 本系统由服务器软件控制平台和fpga硬件处理系统组成，其中fpga硬件处理系统是整个系统的核心部分。系统管理员通过服务器的软件控制平台可以对fpga硬件处理系统进行即时的配置，fpga硬件处理系统按照系统管理员的配置进行工作，并会在检测到异常情况或者检测到用户敏感的流量或者数据包的时候通知服务器，服务器会向管理员发送通知。管理员可以在服务器软件平台上做进一步的分析处理。-The control system consists of server software platform and FPGA hardware processing system, of which FPGA hardware processing system is the core of the whole system. System administrator through the server software control platform FPGA hardware can perform real-time processing system configuration, fpga hardware processing system in accordance with the system administrator s configuration, and will be detected or the detection of anomalies to the user-sensitive traffic or packet when the notification server, the server will send a notification to the administrator. An administrator can in the server software platform for further analytical processing.
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Size: 6212608 |
Author: 李佳琦 |
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Description: ISA板卡，CPLD原理图，altera maxII CPLD芯片。实现运动控制，标准安川伺服器控制接口。-ISA board, CPLD schematic, altera maxII CPLD chip. The realization of motion control, the standard control interface YASKAWA server.
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Size: 1384448 |
Author: xiao |
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Description: VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.-VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.
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Size: 81920 |
Author: James |
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Description: Arbiter unit includes client and server units.
Used for Arbitation of multipliers in Altera FPGA based project.
The code supports several multipliers and several clients with different priorities.-Arbiter unit includes client and server units.
Used for Arbitation of multipliers in Altera FPGA based project.
The code supports several multipliers and several clients with different priorities.
Platform: |
Size: 6144 |
Author: d0238 |
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Description: web server example in vhdl
Platform: |
Size: 64512 |
Author: cheo |
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