Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - VHDL V

Search list

[Other resource] DPLL0227+V+qt6

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 279141 | Author: sss | Hits:

[Other resource] ref-sdr-sdram-vhdl

Description: 标准SDR SDRAM控制器参考设计_verilog_lattice\\sdr_ctrl.v
Platform: | Size: 776642 | Author: 王廷龙 | Hits:

[Other resource] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 250084 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] Vhdl

Description: 这是关于ＶＨＤＬ的一篇文章- This is about a V H D L article
Platform: | Size: 414720 | Author: 朱新平 | Hits:

[VHDL-FPGA-Verilog] vh

Description: 有用的VHDL源代码-useful VHDL source code
Platform: | Size: 590848 | Author: 王新 | Hits:

[VHDL-FPGA-Verilog] 数字频率计实验报告

Description: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Platform: | Size: 144384 | Author: 兰 | Hits:

[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] VGA_Core

Description: 用VHDL语言写的VGA核心,是个很好很齐全的核心,有很多功能.-write VHDL VGA core, is a very good subset of the core, has a lot of functions.
Platform: | Size: 359424 | Author: 朱思华 | Hits:

[VHDL-FPGA-Verilog] Arbiter

Description: Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: | Size: 2048 | Author: 夏虫 | Hits:

[Button control] 4yue11haoxiawu

Description: 1、基于FPGA实现FIR数字滤波器的研究（使用VHDL语言进行编程） 2、多功能单片机下载开发软硬件的设计（利用VB或V C++和C语言）有下载板和下载软件 3、迷你播放器（利用Visual Basic 6.0设计）可以播放多种格式的音乐和电影，以及图片浏览等等 4、小电容小电感测试仪 -1, FPGA-based digital FIR filter (use VHDL program) 2. Multi-function download the software and hardware design development (VB or V C and C language), downloading software and download Plate 3, Player (using Visual Basic 6.0 design) can play multiple formats of music and movies, Photo View and so on four small small inductance capacitor tester
Platform: | Size: 16384 | Author: wangxing | Hits:

[SCM] AD_ASM_AD0832shuzidianyabiaoLED

Description: 数字电压表 AD芯片： 采用8位串行A/D转换器ADC0832。 ● 8位分辨率，逐次逼近型，基准电压为 5V ● 5V单电源供电 ● 输入模拟信号电压范围为 0～5V ● 有两个可供选择的模拟输入通道 显示： 使用三个数码管。 显示范围： 0.00 － 5.10 （单位：V） 连接方式： AD_CLK → P1.0 AD_DAT → P1.1 AD_CS → P3.4 模拟输入 → CH0 (AD_DAT = DO + DI) ADC0832输出最大转换值＝FFH (255) 设定最大测量值＝5.1V 255X=5.1 X=0.02 即先乘2再除以100 （小数点放在第三位数码管）- Digital voltmeter AD chip: Uses 8 serial A/D switch ADC0832.* 8 resolution, gradually approaching, the datum voltage is 5V* the 5V single power source power supply* input simulated signal voltage scope is 0 ~ 5V* has two to be possible to supply the choice the analog input channel Demonstrated: Uses three digital tubes. Demonstrates the scope: 0.00- 5.10 (unit: V) Connection way: AD_CLK-> P1.0 AD_DAT-> P1.1 AD_CS-> P3.4 analog input-> CH0 (AD_DAT = DO DI) ADC0832 output biggest transformation value = FFH (255) establishes greatest observed value = 5.1V 255X=5.1 X=0.02 namely first to ride 2 to eliminate again by 100 (decimal point puts on third digital tube)
Platform: | Size: 7168 | Author: lmhit | Hits:

[Books] ispDesignExpert

Description: 第 一 节 ispDesignEXPERT 简 介 第 二 节 ispDesignEXPERT System 的 原 理 图 输 入 第 三 节 设 计 的 编 译 与 仿 真 第 四 节 ABEL 语 言 和 原 理 图 混 合 输 入 第 五 节 ispDesignEXPERT System 中 VHDL 和Verilog 语 言 的 设 计 方 法 第 六 节 在 系 统 编 程 的 操 作 方 法 第 七 节 ModelSim 的 使 用 方 法 附 录 一 ispDesignEXPERT System 上 机 实 习 题 附 录 二 ispDesignEXPERT System 文 件 后 缀 及 其 含 义-Introduction Section II, section I ispDesignEXPERT ispDesignEXPE RT System III schematic design input to the compilation and simulation fourth ABEL language and schematics mixed input System V ispDesignEXPERT VHDL and Verilog language the statement in section VI Design System Programming methods of operation of the sect ModelSim use is an appendix pDesignEXPERT System attachment that the plane Appendix 2 ispDesignEXPE RT System file extension and its meaning
Platform: | Size: 1292288 | Author: 吴忌 | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库 的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] i2c_master_byte_ctrl0003

Description: 基于VHDL的I2C程序0003,很不错的论文及程序，，大家快下啊-based on the I2C procedures VHDL 0003, a very good paper and procedures, we quickly under ah
Platform: | Size: 3072 | Author: cai | Hits:

[VHDL-FPGA-Verilog] V+m511

Description: M序列编码-M coding sequence
Platform: | Size: 66560 | Author: sss | Hits:

[VHDL-FPGA-Verilog] DPLL0227+V+qt6

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 278528 | Author: sss | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: VHDL教程 ppt版 绪论 第一章 VHDL基本结构 第二章 VHDL语言元素 第三章 VHDL的描述风格 第四章 VHDL的主要描述语句 第五章 组合逻辑电路设计 第六章 时序逻辑电路设计-Ppt version of VHDL Tutorial VHDL Introduction Chapter I Chapter II the basic structure of VHDL language element of VHDL in Chapter III Chapter IV describes the style of the main description language VHDL Chapter V combinational logic circuit design of Chapter VI of sequential logic circuit design
Platform: | Size: 1081344 | Author: 陈松 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: 标准SDR SDRAM控制器参考设计_verilog_lattice\sdr_ctrl.v-Standard SDR SDRAM Controller Reference Design _verilog_latticesdr_ctrl.v
Platform: | Size: 776192 | Author: 王廷龙 | Hits:

[VHDL-FPGA-Verilog] Circuit-Design-with-VHDL---V.Pedroni-(2004)-WW.ra

Description: circuit design with vhdl by Volnei A. Pedroni
Platform: | Size: 5047296 | Author: aaqib | Hits:

[VHDL-FPGA-Verilog] USB-2.0-source-code-by-VHDL

Description: 实现USB2.0，采用VHDL编写，源代码已按类分好-USB 2.0 source code by VHDL
Platform: | Size: 205824 | Author: zzz | Hits:
« 12 3 4 5 6 7 8 9 10 »

CodeBus www.codebus.net