Search - VHDL Viterbi

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[VHDL-FPGA-Verilog] Convolutional encoding and Viterbi decoding with k DL : 0: 卷积码编码和维特比解码当K为7 时供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Update : 2025-02-17 Size : 248kb Publisher : 周小川
[Other Embeded program] SKRETD(low_power) DL : 0: 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
Update : 2025-02-17 Size : 372kb Publisher : xialu
[Communication-Mobile] turbo_VHDL DL : 0: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
Update : 2025-02-17 Size : 151kb Publisher :
[Program doc] Viterbi DL : 0: 三篇关于Viterbi FPGA编译码器的优化设计文档： 1、Viterbi译码器的FPGA设计实现与优化.pdf 2、Viterbi译码器的低功耗设计.pdf 3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf
Update : 2025-02-17 Size : 441kb Publisher : helei_zju
[Communication-Mobile] Viterbi DL : 0: 卷积码（2，1，6），完整的工程文件，已经调试通过-Convolutional code (2,1,6), complete engineering documents have been debugging through
Update : 2025-02-17 Size : 46kb Publisher : jishanyi
[VHDL-FPGA-Verilog] viterbi DL : 0: VHDL 程序，实现vertibe的编码和解码。-VHDL procedures vertibe realize the encoding and decoding.
Update : 2025-02-17 Size : 2kb Publisher : 左麟
[VHDL-FPGA-Verilog] viterbi DL : 0: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Update : 2025-02-17 Size : 61kb Publisher : yaoyongshi
[Compress-Decompress algrithms] 216Viterbi DL : 0: （2，1，6）格式的viterbi译码，软判决，完全的工程文件，可以直接应用于项目。-(2,1,6) format viterbi decoding, soft decision, a complete project file can be directly applied to the project.
Update : 2025-02-17 Size : 46kb Publisher : water206
[Communication] 217viterbi DL : 0: viterbi译码算法的vhdl程序，有注释和各个模块的详细说明。是一篇完整的硕士论文，有源码-viterbi decoding algorithm of VHDL procedures, has comments and a detailed description of each module. Is a complete master
Update : 2025-02-17 Size : 550kb Publisher : Wayne
[Software Engineering] viterbi DL : 0: 适合高速Viterbi译码器的hdl的设计与实现-脢脢潞脧赂脽脣脵Viterbi脪毛脗毛脝梅渭脛hdl渭脛脡猫录脝脫毛脢渭脧脰
Update : 2025-02-17 Size : 433kb Publisher : mediative
[Program doc] viterbi DL : 0: 基于XilinxFPGA的高速Viterbi回溯译码器-Based on retrospective XilinxFPGA high-speed Viterbi decoder
Update : 2025-02-17 Size : 194kb Publisher : mediative
[Program doc] viterbi DL : 0: 高速Viterbi处理器的并行算法和结构-High-speed Viterbi processor parallel algorithm and structure
Update : 2025-02-17 Size : 245kb Publisher : mediative
[VHDL-FPGA-Verilog] viterbi DL : 0: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Update : 2025-02-17 Size : 250kb Publisher : mediative
[Program doc] viterbi DL : 0: 维特比译码器的asic设计的相关论文-Viterbi Decoder asic design related articles
Update : 2025-02-17 Size : 271kb Publisher : mediative
[VHDL-FPGA-Verilog] husw DL : 0: 用VHDL语言设计维特比解码器是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation
Update : 2025-02-17 Size : 1kb Publisher : hsw0320
[VHDL-FPGA-Verilog] Viterbi DL : 0: Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
Update : 2025-02-17 Size : 8kb Publisher : 蔡敏
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Update : 2025-02-17 Size : 3kb Publisher : xiongherui
[VHDL-FPGA-Verilog] viterbi DL : 0: 对于语音信号的Viterbi算法的简单仿真实现在QuartusII下-Viterbi algorithm for speech signals simple simulation to achieve in the next QuartusII
Update : 2025-02-17 Size : 1kb Publisher : 房先生
[VHDL-FPGA-Verilog] Viterbi DL : 0: 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
Update : 2025-02-17 Size : 145kb Publisher : 飞熊
[VHDL-FPGA-Verilog] viterbi DL : 0: 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Update : 2025-02-17 Size : 90kb Publisher : Fengxiaodong

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