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[Other] 基于FPGA的全数字锁相环设计

Description: 用vhdl编写的基于fpga的数字频率计程序算法-prepared using VHDL they simply based on the number of procedures Cymometer Algorithm
Platform: | Size: 286720 | Author: 黄开通 | Hits:

[Embeded-SCM Develop] 16bit_booth_multiplier_STG

Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test
Platform: | Size: 2048 | Author: | Hits:

[Other] EMCRYPTCHIPFORFPGA

Description: 基于FPGA加密芯片设计论文（AES和DES算法）-FPGA-based encryption chip design thesis (AES and DES algorithm)
Platform: | Size: 1068032 | Author: David | Hits:

[Other Embeded program] edge_detector

Description: 基于cpld的数字图像边缘检测算法的实现，vhdl源程序-CPLD-based digital image edge detection algorithm, vhdl source code
Platform: | Size: 1024 | Author: jjaai | Hits:

[VHDL-FPGA-Verilog] djdcf

Description: 在3D图像处理等对运算要求高的领域，高效除法器已成为处理器内必不可少的部件。在分析除法器设计的泰勒级数展开算法基础上，提出了一种新的除法器设计算法。在满足同样精度的情况下，所实现的三级流水线的除法器，与基于泰勒级数展开算法的除法器相比，面积更小，速度更快。-In 3D image processing and so on, demanding area of computing, efficient divider has become essential components inside the processor. In analyzing the divider design Taylor series expansion algorithm based on a new design algorithm divider. Meet the same accuracy in the cases, the three realize the divider line, and based on the Taylor series expansion algorithm divider compared to a smaller area, faster.
Platform: | Size: 157696 | Author: usbusb01 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用VHDL语言编写的一个乘法器校程序 是基于BOOTH算法的 -VHDL language using a multiplier BOOTH school program is based on the algorithm
Platform: | Size: 1024 | Author: 杨天 | Hits:

[VHDL-FPGA-Verilog] Barker

Description: 实现基于逐码移位法的7位巴克码集中插入式搜索算法。-Shift-by-code-based law 7 Barker Code focus on plug-in search algorithm.
Platform: | Size: 1024 | Author: 黄虎 | Hits:

[Software Engineering] baseCORDIC

Description: 基于CORDIC算法数字下变频器设计提出基于CORDIC算法利用FPGA平台数字下变频器设计方案-CORDIC algorithm based on the design of digital down-converter based on CORDIC algorithm using FPGA platform design Digital Downconverter
Platform: | Size: 167936 | Author: elisen | Hits:

[VHDL-FPGA-Verilog] xor_mul

Description: 使用列表法，VHDL语言实现的基于多项式基的有限域乘法器，用于AES算法等对有限域乘法有要求的算法-The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm, such as finite field multiplication algorithm has requested
Platform: | Size: 193536 | Author: zxzx | Hits:

[MPI] butterfly

Description: 附件代码实现了基4FFT的碟形单元运算，是FFT算法的核心部分，并且此碟形单元运算是基于浮点运算的-Annex code base of the dish 4FFT computing unit is the core of the FFT algorithm, and this dish is based on the computing unit of the floating-point operations
Platform: | Size: 4096 | Author: 钟毓秀 | Hits:

[Other] 11

Description: NCO 在信号处理方面有着广泛的应用。而函数发生器是NCO 中的关键部分，本文基 于FPGA 用状态机和流水线方法实现了CORDIC 算法，并取代了传统的ROM 查找表法。 最后通过Quartus II 软件给出仿真结果，验证了理论的正确性。-NCO in the Signal Processing has a wide range of applications. The function generator is a critical part of NCO, the paper-based FPGA using state machine implementation of the Ways and pipelining CORDIC algorithm, and replaces the traditional ROM look-up table method. Finally through the Quartus II software give simulation results to verify the correctness of the theory.
Platform: | Size: 164864 | Author: LEO | Hits:

[VHDL-FPGA-Verilog] CordicNCO

Description: 基于CORDIC算法的，数字控制振荡器的设计。带测试程序，输入一个振荡频率，输出SIN和COS的波形！-Based on the CORDIC algorithm, the digital controlled oscillator design. With test procedures, enter a oscillation frequency, the output waveform SIN and COS!
Platform: | Size: 4096 | Author: 咚咚 | Hits:

[VHDL-FPGA-Verilog] qpsk

Description: 基于vhdl的qpsk算法研究与性能测试-Qpsk of vhdl-based research and performance testing algorithm
Platform: | Size: 569344 | Author: matt | Hits:

[Crack Hack] khalil2006_true_random_number_generator

Description: a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are required to generate public/private key pairs for asymmetric algorithm such as RSA and symmetric algorithm such as AES.
Platform: | Size: 418816 | Author: Hassan Abdelaziz | Hits:

[Program doc] 2fft

Description: 基2FFT算法实现改进的一篇很好的文章,有利于傅立叶变换的理解-2FFT-based algorithm to improve a very good article, and is conducive to the understanding of Fourier Transform
Platform: | Size: 250880 | Author: 任杏 | Hits:

[VHDL-FPGA-Verilog] aescore

Description: 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
Platform: | Size: 195584 | Author: 李华 | Hits:

[Embeded-SCM Develop] DSP_Algorithms

Description: 基于FPGA的DSp算法转换方法-由matlab程序转换为VHDL-FPGA-based algorithm for DSp conversion method- from the matlab program is converted to VHDL
Platform: | Size: 147456 | Author: dtcxh | Hits:

[Windows Develop] 7941955BasicRSA

Description: The RSA algorithm can be used for both public key encryption and digital signatures. Its security is based on the difficulty of factoring large integers. -The RSA algorithm can be used for both public key encryption and digital signatures. Its security is based on the difficulty of factoring large integers.
Platform: | Size: 9216 | Author: parvathalu | Hits:

[VHDL-FPGA-Verilog] VHDL-test-code-divider

Description: VHDL实验代码：除法器，是一个基于VHDL语言开发的小程序，是关于除法的算法，比较实用-VHDL test code: divider, is a VHDL-based language developed by a small program, on the division algorithm, more practical
Platform: | Size: 1024 | Author: Johonson | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 基于VHDL的数字倍频器设计，这里只提供个算法，希望对你的编程有所启发。-Vhdl based on the number of times the frequency of the design,Here only to provide an algorithm, hope for your programming has been inspired.
Platform: | Size: 331776 | Author: 杜维轩 | Hits:
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