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[VHDL-FPGA-Verilog] FIR_vhdl

Description: 基本FIR滤波器的VHDL源代码及其测试程序。-basic FIR filter VHDL source code and testing procedures.
Platform: | Size: 1024 | Author: qjyong | Hits:

[VHDL-FPGA-Verilog] FIR_beh

Description: FIR滤波器的行为级VHDL源代码，可以任意修改滤波器级数，滤波器系数的精度为16比特。-FIR filter behavioral VHDL source code, which could be amended filter series. The filter coefficients for the 16-bit accuracy.
Platform: | Size: 1024 | Author: 郭兴波 | Hits:

[Software Engineering] filter-vhdl-code

Description: filter-vhdl-code.rar为滤波器的完整VHDL程序，可用于IIR与FIR滤波器的仿真与验证实现，包括代码综合。使用版本为ISE6.3.-filter-vhdl-code.rar for the integrity of filter VHDL procedures, can be used for IIR and FIR filters realize simulation and verification, including an integrated code. Use version ISE6.3.
Platform: | Size: 173056 | Author: petri | Hits:

[VHDL-FPGA-Verilog] fir_16

Description: fir滤波器-verilog，基于verilog的fir滤波器源码-fir filter-verilog, the fir filter based on the Verilog source code
Platform: | Size: 742400 | Author: zhc | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] coeff_rom_1_6

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[VHDL-FPGA-Verilog] coeff_rom_2_5

Description: FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation
Platform: | Size: 2048 | Author: surya | Hits:

[Other] fir_16

Description: vhdl代码 实现16阶fir滤波器，可以仿真通过-vhdl code fir filter stage 16 can be adopted simulation
Platform: | Size: 3072 | Author: sumli | Hits:

[Software Engineering] filter_final

Description: compiled vhdl code for fir filter
Platform: | Size: 1210368 | Author: surya | Hits:

[VHDL-FPGA-Verilog] beta

Description: Fir verilog code implemented to find out the output of fir filter
Platform: | Size: 1024 | Author: dheeru | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR在FPGA中的VHDL代码实现教程-FIR in FPGA code in VHDL Tutorial
Platform: | Size: 20480 | Author: Mr Yang | Hits:

[VHDL-FPGA-Verilog] fir

Description: code for fir filter see it is from altera site.-code for fir filter see it is from altera site.
Platform: | Size: 26624 | Author: bris | Hits:

[VHDL-FPGA-Verilog] fir

Description: 16阶FIR VHDL程序并附带testbench，并有简单流水线设计！-16 Tap FIR vhdl code with testbench and pipelining design
Platform: | Size: 352256 | Author: hongwan | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
Platform: | Size: 4096 | Author: 周州 | Hits:

[Other] f

Description: vhdl code for FIR filter
Platform: | Size: 1024 | Author: vovanich | Hits:

[VHDL-FPGA-Verilog] fir

Description: vhdl code for fir filter
Platform: | Size: 1024 | Author: praba | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

[VHDL-FPGA-Verilog] CSDmultiplier

Description: Code for CSD Multiplier
Platform: | Size: 1024 | Author: yuvi | Hits:

[VHDL-FPGA-Verilog] fir

Description: vhdl code for fir filter
Platform: | Size: 1024 | Author: lekshmi | Hits:

[VHDL-FPGA-Verilog] fir

Description: this is an vhdl code for fir filter-this is an vhdl code for fir filter....
Platform: | Size: 7168 | Author: datta | Hits:
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