Description: Verilog 下脉冲发生器的源代码,可用于模拟三相交流电过零点,主要用于调试一些类似SVC(无功补偿)控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms Platform: |
Size: 763904 |
Author:huangyongbing |
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Description: VHDL小程序,其中包含了bcd码转换成格雷码、寄存器的简单设计(并入串出移位寄存器、串入串出移位寄存器)以及脉冲发生器的VHDL实现。适合于基础的VHDL入门。-VHDL small program, which includes a bcd code into Gray code, register for a simple design (String into a shift register, the string into the string out of the shift register) and a pulse generator VHDL implementation. Suitable for basic VHDL entry. Platform: |
Size: 304128 |
Author:鸿雨 |
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