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[DSP program] apps

Description: DM6446的codec engine 应用端算法源码，包括video，audio，speech等开发实例。-DM6446-side of the codec engine algorithm source applications, including video, audio, speech, such as the development of examples.
Platform: | Size: 1067008 | Author: bing | Hits:

[TCP/IP stack] sample_frame_app

Description: TCP/IP Frame Package distributor engine
Platform: | Size: 208896 | Author: You | Hits:

[TCP/IP stack] sample_ip_app

Description: tcp ip IP layer distributor engine
Platform: | Size: 398336 | Author: You | Hits:

[TCP/IP stack] sample_udp_app

Description: TCP/IP UDP layer distributor engine
Platform: | Size: 717824 | Author: You | Hits:

[VHDL-FPGA-Verilog] Moteur_test

Description: Engine for a test memory CY7C1062AV-Engine for a test memory CY7C1062AV33
Platform: | Size: 1024 | Author: guigui | Hits:

[VHDL-FPGA-Verilog] tb_Moteur_test

Description: Test Bench for an engine code VHDL for CY7C1062AV-Test Bench for an engine code VHDL for CY7C1062AV33
Platform: | Size: 1024 | Author: guigui | Hits:

[VHDL-FPGA-Verilog] 1DCT_VHDL

Description: VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.-VHDL Behavioral Model for 1D DCT operation Algorithm : Calculates the 1D DCT coefficients. DCT Points range from 8 to 32. There is double buffering at the input, to allow continuous usage of DCT engine.
Platform: | Size: 11264 | Author: NULL | Hits:

[matlab] Rocket

Description: 很好的高速口的设计资料，很好的高速口的设计资料 很好的高速口的设计资料-In design of large-scale access convergence router(hereafter referred to ACR) forwarding engine, the Xilinx Virtex-4 FPGA!s RocketI/O r multi-gigabit transceiver is used to satisfy the need of high speed and steady interface between forwarding engine and switch fabric. This pape proposes an assistant channel bonding method for solving the difficult problem of channels-bonding synchronization. Experimental results show the
Platform: | Size: 272384 | Author: guoguo | Hits:

[VHDL-FPGA-Verilog] can_latest[1].tar

Description: CAN，全称“Controller Area Network”，即控制器局域网，是国际上应用最广泛的现场总线之一。最初，CAN被设计作为汽车环境中的微控制器通讯，在车载各电子控制装置ECU之间交换信息，形成汽车电子控制网络。比如：发动机管理系统、变速箱控制器、仪表装备、电子主干系统中，均嵌入CAN控制装置。 -CAN, full name of the " Controller Area Network" , the Controller Area Network, is internationally the most widely used field bus. Initially, CAN is designed as a vehicle environment, the micro-controller communications, in-vehicle electronic control unit ECU of the exchange of information between the formation of automotive electronic control network. For example: engine management systems, transmission controllers, instrumentation and equipment, electronic backbone of the system are embedded CAN control.
Platform: | Size: 1149952 | Author: zhaohaiting | Hits:

[VHDL-FPGA-Verilog] pidviaVhdl

Description: VHDL实现PID发动机转速控制,内置程序说明，一目了然-VHDL realize PID control engine speed, built-in program instructions at a glance
Platform: | Size: 3072 | Author: 焱斐然 | Hits:

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