Search - VHDL led Counter

[File Operate] VHDL_clock

Description: 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Platform: | Size: 105273 | Author: lianbin | Hits:

[Embeded-SCM Develop] vhdlshiyan

Description: 本文为采用VHDL编写的程序及报告。步骤如下：1设计三位二进制计数器程序二:设计一驱动循环显示7位数字 2编写LED控制程序如下： 3设计采用原理图方式如下: -VHDL paper prepared for the introduction of procedures and reports. Steps are as follows : Design of a binary counter three two procedures : Design of a drive cycle show seven figures prepared two LED control procedures are as follows : three designs diagram as follows :
Platform: | Size: 296936 | Author: 梁兵 | Hits:

[File Format] VHDL_clock

Description: 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Platform: | Size: 105472 | Author: lianbin | Hits:

[Embeded-SCM Develop] vhdlshiyan

Description: 本文为采用VHDL编写的程序及报告。步骤如下：1设计三位二进制计数器程序二:设计一驱动循环显示7位数字 2编写LED控制程序如下： 3设计采用原理图方式如下: -VHDL paper prepared for the introduction of procedures and reports. Steps are as follows : Design of a binary counter three two procedures : Design of a drive cycle show seven figures prepared two LED control procedures are as follows : three designs diagram as follows :
Platform: | Size: 296960 | Author: 梁兵 | Hits:

[VHDL-FPGA-Verilog] freqm

Description: a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
Platform: | Size: 12288 | Author: wangfeng | Hits:

[VHDL-FPGA-Verilog] t1

Description: 带清零和重置功能的十进制计数器，可以用LED灯显示结果-Cleared and reset with the decimal counter, can use LED lights display the results
Platform: | Size: 1011712 | Author: 孟明川 | Hits:

[VHDL-FPGA-Verilog] Led

Description: 本程序有效的防止了按键的抖动，可以移植于各种需要按键防抖的程序，本程序是功能为按键防抖16进制减法计数器-debounced counter VHDL
Platform: | Size: 288768 | Author: hide tyou | Hits:

[VHDL-FPGA-Verilog] db0358fc-1f16-4f07-9f0f-defb77998bb1

Description: fpga实现简单的计数器功能，用vhdl写的，有一个LED-fpga simple counter function
Platform: | Size: 580608 | Author: zx | Hits:

[VHDL-FPGA-Verilog] PPT

Description: 大学EDA课程的课件以及课后部分习题的程序。包括最基本的加法器、计数器、LED显示以及部分高级VHDL程序。-University of EDA software programs, as well as some after-school exercise procedures. Including the most basic adder, counter, LED display, as well as some high-level VHDL procedures.
Platform: | Size: 8547328 | Author: 寂静的璀璨 | Hits:

[VHDL-FPGA-Verilog] ADC_Fre_counter_LED_keyboard

Description: FPGA tlc082０采样控制　高精度测频　ＬＥＤ键盘显示　ＶＨＤｌ　调试与ＥＰ１Ｃ３-FPGA vhdl ADC LED keyboard frequency counter test
Platform: | Size: 2595840 | Author: Albert Sun | Hits:

[Embeded-SCM Develop] lab8

Description: 此實驗中我們將量測人的反應時間，由於人的反應時間遠比起內建CLOCK的週期長的多，因此要對CLOCK做除頻的動作方可適用，並方便於計數器的計算與七段顯示器的呈現。實驗內容為，當看到LED亮起時，立即做出反應將計數器停下，並顯示出當時計數器之時間。計數器以兩位數 BCD counter來實現並將結果顯示於七段顯示器上。-Volume in this experiment we will test people' s reaction time, because people' s reaction time is far longer than the built-in multi-CLOCK cycle, and therefore the frequency of CLOCK to do except be applicable to the action, and facilitate in the total number of device Computing and seven-segment display rendering. Test content, when you see LED Leung from time to time, to respond immediately to stop the total number of devices and demonstrate the total number of devices was the time. Total number of devices with two-bit number of BCD counter future to achieve the results shown in the seven-segment display.
Platform: | Size: 141312 | Author: 徐小華 | Hits:

[VHDL-FPGA-Verilog] 10512210247008

Description: 该数字式相位测量仪以单片机 (89c52) 为核心 , 通过高速计数器 CD4040 为计数器计算脉冲个数从 , 而达到计算相位的要求 , 通过 8279 驱动数码管显示正弦波的频率，不采用一般的模拟的振动器产生 , 而是采用单片机产生 , 从而实现了产生到显示的数字化 . 具有产生的频率精确 , 稳定的特点 . 相移部分采用一般的 RC 移相电路 , 节省了成本。-The digital phase-measuring instrument in order to microcontroller (89c52) as the core, high-speed counter CD4040 as counter to calculate the number of pulses from, to achieve the requirements of the calculation phase, through 8279 driving LED display sine wave frequency, non-use of simulation in general vibrators produce, instead of using SCM generation, in order to achieve the creation to display digital. has produced a frequency accuracy and stability characteristics. phase shift part of the application of the normal RC phase-shift circuit, saving costs.
Platform: | Size: 145408 | Author: 包进辉 | Hits:

[VHDL-FPGA-Verilog] sram

Description: 数据存储和读取电路以一个双端口SRAM为中心，用二进制计数器产生存取地址、以十进制计数器产生欲存储的数据，读出的数据经过LED七段译码，送LED数码管显示-Data storage and reading circuit in a dual-port SRAM as the central access address generated using a binary counter to generate For decimal counter data stored, read out the data through LED seven-segment decoder, sending LED digital display
Platform: | Size: 434176 | Author: william | Hits:

[VHDL-FPGA-Verilog] 7

Description: 调用总共四个计数器（两个六进制，两个十进制，六进制计数器可由实验五的程序做简单修改而成）串起来构成异步计数器，计数器的值，通过实验九串行扫描输出。用1Hz连续脉冲作为输入，这样就构成一个简单的1h计时器。带一个清零端。输入：连续脉冲，逻辑开关；输出：七段LED。 -Called a total of four counters (two six-band, two decimal, hexadecimal counter by six experimental procedure to do five simple changes made) string together to form an asynchronous counter, the counter, and by nine serial scan test output. 1Hz pulse with a continuous input, it constitutes a simple timer 1h. With a clear end. Input: Continuous pulse, logic switches output: seven-segment LED.
Platform: | Size: 6144 | Author: 李小勇 | Hits:

[VHDL-FPGA-Verilog] vhdlcoder

Description: 本文件夹包含了16个VHDL 编程实例，仅供读者编程时学习参考。一、四位可预置75MHz -BCD码（加/减）计数显示器（ADD-SUB）。二、指示灯循环显示器（LED-CIRCLE) 三、七人表决器vote7 四、格雷码变换器graytobin 五、1位BCD码加法器bcdadder 六、四位全加器adder4 七、英语字母显示电路 alpher 八、74LS160计数器74ls160 九、可变步长加减计数器 multicount 十、可控脉冲发生器pluse 十一、正负脉宽数控调制信号发生器pluse width 十二、序列检测器string 十三、出租车计费器spend 十四、数字秒表selclk 十五、抢答器 first -This folder contains 16 examples of VHDL programming, only for readers to learn programming reference. 1, 4 Preset 75MHz-BCD code (plus/minus) count display (ADD-SUB). Second, light cycle display (LED-CIRCLE) 3, seven voting machines vote7 4, Gray code converter graytobin 5, a BCD code adder bcdadder six, four full adder adder4 seven or eight English letter display circuit alpher , 74LS160 counter 74ls160 9, variable-step addition and subtraction counters multicount 10, controllable pulse generator pluse 11, positive and negative pulse width modulation signal generator pluse width of NC 12, sequence detector string 13, a taxi billing spend 14 devices, digital stopwatch selclk 15, Responder first
Platform: | Size: 59392 | Author: 李磊 | Hits:

[VHDL-FPGA-Verilog] VHDL-3BCD

Description: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Platform: | Size: 56320 | Author: will li | Hits:

[VHDL-FPGA-Verilog] VHDL-LED

Description: 设计一个带计数使能、异步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示-Design a counter with enable and asynchronous reset, brought by a six-bit output of the binary counter, counting the results from the common cathode seven segment display
Platform: | Size: 59392 | Author: ds18b20 | Hits:

[Post-TeleCom sofeware systems] Decimal-Counter

Description: 十进制计数器（异步置数）及七段数码管显示系统，VHDL语言-Decimal Counter (Asynchronous Set the number) and the seven-segment LED display system, VHDL language
Platform: | Size: 1024 | Author: 真夏 | Hits:

[VHDL-FPGA-Verilog] VHDL代码

Description: 实现简单的电子拔河比赛，即两按键模拟，计数器计数，比较器进行比较，最后通过LED灯进行直观显示(To achieve a simple tug of war competition, that is, two button analog, counter count, comparator comparison, and finally through the LED lamp for visual display)
Platform: | Size: 1024 | Author: 很看好 | Hits:

[VHDL-FPGA-Verilog] piano

Description: 电子琴原创作业 VHDL 采用计数器分频，内含简单儿歌数首，爱迪克ＥＤＡ实验箱，有数码管与ＬＥＤ显示，采用键盘式输出，两行，中音高音。(Electronic piano original work VHDL, using counter frequency division, contains a few simple nursery rhyme, Edik EDA experimental box, there are digital tube and LED display, using keyboard output, two lines, alto treble.)
Platform: | Size: 1101824 | Author: qengleikangjen | Hits:

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[File Operate] VHDL_clock

[Embeded-SCM Develop] vhdlshiyan

[File Format] VHDL_clock

[Embeded-SCM Develop] vhdlshiyan

[VHDL-FPGA-Verilog] freqm

[VHDL-FPGA-Verilog] t1

[VHDL-FPGA-Verilog] Led

[VHDL-FPGA-Verilog] db0358fc-1f16-4f07-9f0f-defb77998bb1

[VHDL-FPGA-Verilog] PPT

[VHDL-FPGA-Verilog] ADC_Fre_counter_LED_keyboard

[Embeded-SCM Develop] lab8

[VHDL-FPGA-Verilog] 10512210247008

[VHDL-FPGA-Verilog] sram

[VHDL-FPGA-Verilog] 7

[VHDL-FPGA-Verilog] vhdlcoder

[VHDL-FPGA-Verilog] VHDL-3BCD

[VHDL-FPGA-Verilog] VHDL-LED

[Post-TeleCom sofeware systems] Decimal-Counter

[VHDL-FPGA-Verilog] VHDL代码

[VHDL-FPGA-Verilog] piano

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