Search - VHDL nand

[Other resource] vhdl-core-Kopie_von_mem32_vhd

Description: vhdl 模块对nand flash控制，实现了FPGA对NAND FLASH直接读写控制。
Platform: | Size: 4173 | Author: 骑士 | Hits:

[Embeded Linux] NAND FLASH VHDL

Description: nand flash的VHDL编程设计
Platform: | Size: 1587101 | Author: mxl2003305730@sina.com | Hits:

[Other] NAND_Controller_and_ECC_VHDL

Description: NAND Flash Controller & ECC VHDL Code-NAND Flash Controller
Platform: | Size: 22528 | Author: | Hits:

[Embeded-SCM Develop] xapp354_vhdl

Description: 用CPLD实现NAND FLASH接口的VHDL源码-Using CPLD realize NAND FLASH interface VHDL source code
Platform: | Size: 871424 | Author: xillinx | Hits:

[VHDL-FPGA-Verilog] vhdl-core-Kopie_von_mem32_vhd

Description: vhdl 模块对nand flash控制，实现了FPGA对NAND FLASH直接读写控制。-VHDL module nand flash control, the FPGA to realize the direct read and write control NAND FLASH.
Platform: | Size: 4096 | Author: 骑士 | Hits:

[VHDL-FPGA-Verilog] hdl

Description: 用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制-Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Platform: | Size: 6144 | Author: 刘义春 | Hits:

[ARM-PowerPC-ColdFire-MIPS] FLASHcontrollercode

Description: NAND FLASH控制器源代码（测试通过）-NAND FLASH controller source code (the test)
Platform: | Size: 2048 | Author: 王一 | Hits:

[ARM-PowerPC-ColdFire-MIPS] nand_flash_ctl

Description: nand flash control logic
Platform: | Size: 4096 | Author: yinxuebing | Hits:

[VHDL-FPGA-Verilog] ECCgenAndLoc

Description: 基于xilinx ISE环境开发的VHDL的NAND flash ECC 实现,eccGen256Byte 文件夹为ECC 产生程序，EccErrLoc文件夹为ECC错误定位程序。-Xilinx ISE environment based on the development of VHDL the NAND flash ECC to achieve, eccGen256Byte folder produced for the ECC procedures, EccErrLoc folder location for the ECC error procedures.
Platform: | Size: 1504256 | Author: 卓智海 | Hits:

[Other] jmf602

Description: SATA接口SSD控制器介绍以及支持NAND FLASH列表，目前比较流行的低成本SSD方案．-SATA interface SSD controller and support for NAND FLASH, introduced a list of currently popular low-cost SSD program.
Platform: | Size: 247808 | Author: gxliu | Hits:

[VHDL-FPGA-Verilog] NAND_Controller_and_ECC_VHDL

Description: 完整的控制ｎａｎｄ读写的ｖｈｄｌ程序模块，包含了无缝连接的ｅｃｃ校验程序，非常值得学习借鉴-NAND read and write complete control of the VHDL program modules, including the seamless connection of ecc checking procedures, very worthwhile to learn from
Platform: | Size: 22528 | Author: yangyu | Hits:

[VHDL-FPGA-Verilog] NANDflash

Description: NAND型闪存接口程序里面包含了datasheet以及测试程序 -NAND flash memory interface program
Platform: | Size: 846848 | Author: jiangyuhang | Hits:

[VHDL-FPGA-Verilog] NANDFLASH

Description: 用VHDL开发的NANDFLASH的读写程序,给出 NANDFLASH的时序正确的读写-NANDFLASH developed using VHDL to read and write the procedures, timing NANDFLASH give the correct reading and writing
Platform: | Size: 31744 | Author: mxc | Hits:

[Driver Develop] 123456

Description: NAND型Flash在大容量存储回放系统中的应用-Flash
Platform: | Size: 53248 | Author: zhongjian | Hits:

[Other] verilog__nand

Description: verilog source code nand gate
Platform: | Size: 1024 | Author: hamsik yoo | Hits:

[VHDL-FPGA-Verilog] RS_5_3_GF256

Description: 用于NAND FLASH CONTROLLER 中的 ecc 各个模块VHDL代码-NAND FLASH CONTROLLER for ecc modules in VHDL code
Platform: | Size: 197632 | Author: 陈佳宜 | Hits:

[FlashMX] Nand_verilog

Description: NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array. To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.-NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array. To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Platform: | Size: 870400 | Author: anirudhh | Hits:

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