Description: 在信息处理中，特别是实时视频图像处理中，通常都要对实现视频图像进行处理，而这首先必须设计大容量的存储器，同步动态随机存储器SDRAM虽然有价格低廉、容量大等优点，但因SDRAM的控制结构复杂，常用的方法是设计SDRAM通用控制器，这使得很多人不得不放弃使用SDRAM而使用价格昂贵的SRAM。为此，笔者在研究有关文献的基础上，根据具体情况提出一种独特的方法，实现了对SDRAM的控制，并通过利用FPGA控制数据存取的顺序来实现对数字视频图像的旋转，截取、平移等实时处理。-In information processing, especially real-time video image processing usually have to deal with video images, which must first be designed large-capacity memory, synchronous dynamic random access memory SDRAM Although there are low cost, large capacity, etc., but SDRAM control structure of the complex, commonly used method is to design generic SDRAM controller, which makes a lot of people had to abandon the use of SDRAM and the use of expensive SRAM. To this end, the authors examine the literature based on the specific situation in a unique way to realize the control of SDRAM, and control data through the use of FPGA to realize the order of access to digital video image rotation, interception, translation, such as real-time processing. Platform: |
Size: 137216 |
Author:赵明玺 |
Hits:
Description: 此代码用于产生系统设计仿真阶段需要的仿真数据，运行的结果是一系列随机数。编译后可生成数据产生模块，在其他工程中之间调用之作为数据输入即可，对vhdl涉及仿真有一定的帮助-This code is used for creating a system design simulation stage of simulation data, the results of running a series of random numbers. Compiler can generate data generated modules, in other works as a call between the data input to the VHDL simulation involves a certain degree of help Platform: |
Size: 35840 |
Author:王弋妹 |
Hits:
Description: RISC状态机由三个功能单元构成：处理器、控制器和存储器。
RISC状态机经优化可实现高效的流水线操作。
RISC 中的数据线为16位。
在数据存储器中的0到15的位置放置16个随机数，求16个数的和，放在数据存储器的16、17的位置，高位在前
对这16个数进行排序，从大到小放置在18到33的位置
求出前16个数的平均数，放在34的位置
基本指令有NOP, ADD, SUB, AND, RD, WR, BR,BC。
因为采用16位指令，有扩充的余地。-RISC state machine consists of three functional modules: processor, controller and memory. RISC state machine can be realized by optimizing the efficient pipelining. RISC data in line 16. In the data memory in the 0-15 position placed 16 random numbers, and the number 16 and, on the data memory of the 16,17 position, the previous high of 16 the number of these sort, smallest place in the 18-33 position to derive the average number of the top 16, on the location of 34 basic instructions are NOP, ADD, SUB, AND, RD, WR, BR, BC. Because the use of 16-bit instructions, there is room for expansion. Platform: |
Size: 129024 |
Author:lyn |
Hits:
Description: In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear.
and more sevear is such distortion is random.
To handle this, multipath affected channels require Equalizers at receaver end.
such equalizer uses different learning Algorithms for identifying channels continuously.
This project is VHDL implementation of LMS learning algorithm with pipelined architecture. so this implementation can work with higher data rates with less clock speed requirments and so with less power consumpiton
It uses Fixed point arithmatic blocks for filtering so suitable for coustom asic. Platform: |
Size: 14336 |
Author:Arun |
Hits:
Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface
- use external RX and TX clocks
- Start and end of frame pattern generation
- Start and end of frame pattern checking
- Idle pattern generation and detection (all ones)
- Idle pattern is assumed only after the end of a frame which is signaled by an abort signal
- Zero insertion
- Abort pattern generation and checking
- Address insertion and detection by software
- CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used)
- FIFO buffers and synchronization (External)
- Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted)
- Q.921, LAPB and LAPD compliant.
- For complete specifications refer to spec document
Platform: |
Size: 188416 |
Author: |
Hits:
Description: 根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中，从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织，同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can also be deinterleaving deinterleaving pattern, the same algorithm. Platform: |
Size: 1024 |
Author:源天 |
Hits:
Description: vhdl实现FSK调制，本次毕业设计的数据速率 1.2kb/s，要求产生一个1.2kHz的正弦信号，对正弦信号每周期取100个采样点，因此要求产生3个时钟信号：1.2kHz（数据速率）、120kHz（产生1.2kHz正弦信号的输入时钟）、240kHz（产生2.4kHz正弦信号的输入时钟）。基准时钟已由一个外部时钟120MHz提供，要得到前面三种时钟，就需要首先设计一个模50的分频器产生240kHz信号，再设计一个二分频器，生产一个120kHz的信号，然后再前面的基础上再设计一个模100的分频器，用来产生1.2kHz的随机信号产生速率。-vhdl achieve FSK modulation, the graduate design data rate of 1.2kb/s to produce a sinusoidal signal of 1.2kHz, take the 100 sampling points per cycle of the sinusoidal signal, thus requiring to produce the three clock signals: 1.2 kHz (data rate , 120kHz, a 1.2kHz sine input clock signal), 240kHz (a 2.4kHz sine signal input clock). 120MHz reference clock has been an external clock to get the first three clock, you need to first design a mold 50 of the divider to produce a 240kHz signal, re-design of a two frequency divider to produce a 120kHz signal, and then the front of the base on the re-design of a mold 100 of the divider used to generate the 1.2kHz random signal generator rate. Platform: |
Size: 1024 |
Author:杨 |
Hits:
Description: This page of VHDL source code covers read RAM and write to RAM vhdl code.
RAM stands for Random Access memory.It is a form of data storage for various applications.
1K refers 10 lines used for Address bus (as 2^10=1024)
8 refers Data Bus lines are 8
Hence, each location can store 8 bits (i.e. 1 byte each)
ADR: in std_logc_vector (9 downto 0)
D: inout std_logic_vector (7 downto 0)
CS: in std_logic
OE: in std_logic
WR: in std_logic-This page of VHDL source code covers read RAM and write to RAM vhdl code.
RAM stands for Random Access memory.It is a form of data storage for various applications.
1K refers 10 lines used for Address bus (as 2^10=1024)
8 refers Data Bus lines are 8
Hence, each location can store 8 bits (i.e. 1 byte each)
ADR: in std_logc_vector (9 downto 0)
D: inout std_logic_vector (7 downto 0)
CS: in std_logic
OE: in std_logic
WR: in std_logic Platform: |
Size: 1024 |
Author:ss |
Hits:
Search - VHDL random data