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[Other resource] router

Description: VHDL router16通路选择器 基于实际模型的设计
Platform: | Size: 2467 | Author: wuxiao | Hits:

[Internet-Network] deskew

Description: 本代码用于路由器的线路接口卡中，实现到达数据位的位间调整，使时钟边沿位于数据窗的中心位置-The code for the router
Platform: | Size: 3072 | Author: yang | Hits:

[Internet-Network] showproc_cpu

Description: 对cisco路由器的命令模拟 -To the cisco router simulation commands
Platform: | Size: 45056 | Author: dongwenxue | Hits:

[ARM-PowerPC-ColdFire-MIPS] router

Description: VHDL router16通路选择器 基于实际模型的设计 -VHDL router16 channel selector design based on the actual model
Platform: | Size: 2048 | Author: wuxiao | Hits:

[VHDL-FPGA-Verilog] router_routing

Description: 片上网络NOC基于fpga实现的，routing模块。-NOC-chip networks realized fpga-based, routing module.
Platform: | Size: 1024 | Author: 巴音 | Hits:

[Other] netfpga_base_beta_1_2_5_2_CentOS4.tar

Description: centOS4与netfpga的协同工程文件，可以提高router的处理速度-centOS4 collaborative projects with netfpga documents, can improve processing speed router
Platform: | Size: 3366912 | Author: jingjie | Hits:

[Other] netfpga_rcp_router_1_0_0.tar

Description: 以NetFPGA为开发平台的路由器，可以在开发板上综合为真正的路由器！-NetFPGA a platform for the development of the router, can be integrated in the development of on-board router for real!
Platform: | Size: 1846272 | Author: jingjie | Hits:

[matlab] Rocket

Description: 很好的高速口的设计资料，很好的高速口的设计资料 很好的高速口的设计资料-In design of large-scale access convergence router(hereafter referred to ACR) forwarding engine, the Xilinx Virtex-4 FPGA!s RocketI/O r multi-gigabit transceiver is used to satisfy the need of high speed and steady interface between forwarding engine and switch fabric. This pape proposes an assistant channel bonding method for solving the difficult problem of channels-bonding synchronization. Experimental results show the
Platform: | Size: 272384 | Author: guoguo | Hits:

[Other] in_combine

Description: 高速路由器中，四路2.5Gbps数据合并成一路10Gbps数据。-High-speed router, four 2.5Gbps data merged into the way 10Gbps data.
Platform: | Size: 3072 | Author: gluttoni | Hits:

[e-language] fifo

Description: This VHDL code for FIFO that is used in a NOC router-This is VHDL code for FIFO that is used in a NOC router
Platform: | Size: 1024 | Author: Anish Goel | Hits:

[e-language] router

Description: This VHDL code for router used in FPGA based system -This is VHDL code for router used in FPGA based system
Platform: | Size: 1024 | Author: Anish Goel | Hits:

[VHDL-FPGA-Verilog] intf_wrapper

Description: This a vhdl code for router code for testing write and read transfers code-This is a vhdl code for router code for testing write and read transfers code
Platform: | Size: 1024 | Author: usha | Hits:

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