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[Crack Hack] scrambler

Description: 扰码程序，利用VHDL语言实现，适合各种通信系统的扰码。
Platform: | Size: 738841 | Author: 徐劲松 | Hits:

[SourceCode] V35_Descrambler_Scrambler

Description: ITU-T V35 加扰/解扰 VHDL代码 ITU-T V35 Scrambler Descrambler
Platform: | Size: 1270 | Author: lake@wancom.com.cn | Hits:

[Other] SC-DSC

Description: 数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术，就是不增加多余度而扰乱信号，改变数字信号的统计特性，使其近 似于白噪声统计特性的一种技术。这种技术的基础是建立在反馈移位寄存器序 列（伪随机序列）理论之上的。解扰是加扰的逆过程，恢复原始的数字信号。 如果数字信号具有周期性，则信号频谱为离散的谱线，由于电路的非线 性，在多路通信系统中，这些谱线对相邻信道的信号造成串扰。而短周期信号 经过扰码器后，周期序列变长，谱线频率变低，产生的非线性分量落入相邻信 道之外，因此干扰减小。 在有些数字通信设备中，从码元“0”和“1”的交变点提取定时信息，若 传输的数字信号中经常出现长的“1”或“0”游程，将影响位同步的建立和保 持。而扰码器输出的周期序列有足够多的“0”、“1”交变点，能够保证同步 定时信号的提取。 -digital communication system design and performance and the transmission of digital signals on the statistical characteristics. The so-called scrambling technology is not to increase the degree to disrupt redundant signal, digital signal change the statistical properties it is similar to white noise statistical characteristics of a technology. This technology is based on feedback shift register sequences (pseudo-random sequence) of the above theory. Decryption is the reverse of the scrambling process, the restoration of the original digital signal. If the digital signal is cyclical, the signal spectrum of discrete lines, as the nonlinear circuit, in multi-channel communication system, these lines of the adjacent channel signal causing crosstalk. And the short-cycle signal after scrambling
Platform: | Size: 113664 | Author: 葛岭泉 | Hits:

[Crack Hack] scrambler

Description: 扰码程序，利用VHDL语言实现，适合各种通信系统的扰码。-Scrambler procedures, the use of VHDL language, suitable for a variety of communication systems Scrambler.
Platform: | Size: 738304 | Author: 徐劲松 | Hits:

[VHDL-FPGA-Verilog] bluetooth

Description: ip核，蓝牙bluetooth的fpga硬件实现-ip nuclear, Bluetooth bluetooth realize the FPGA hardware
Platform: | Size: 16384 | Author: 惠普 | Hits:

[Communication-Mobile] scrambleanddescrambler

Description: 适合802.11a的scrambler与descrambler的设计，适合OFDM系统设计的初学者，有testbench可供参考-The scrambler and descrambler for 802.11a design, OFDM system design for beginners, there are available for reference testbench
Platform: | Size: 1024 | Author: jiaqi yuan | Hits:

[VHDL-FPGA-Verilog] SCRAMBLER

Description: 32位扰码器的verilog代码，编译通过-The Verilog code of 32_bit scrambler
Platform: | Size: 1024 | Author: 朱猪 | Hits:

[Com Port] scrambler

Description: 数字通信的扰码程序，保证二进制０１的数量基本相同-Digital communications scrambler procedures to ensure the same number of binary 01
Platform: | Size: 1024 | Author: chenxuhui | Hits:

[VHDL-FPGA-Verilog] DATA_scramble

Description: 扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation
Platform: | Size: 1024 | Author: | Hits:

[Books] bmul32par

Description: scrambler for IEEE 802.16 PHY
Platform: | Size: 1024 | Author: user1 | Hits:

[VHDL-FPGA-Verilog] scrambler_17

Description: this parallel scrambler verilog code -this is parallel scrambler verilog code
Platform: | Size: 322560 | Author: rakhi | Hits:

[VHDL-FPGA-Verilog] screw

Description: 一个好用的扰码器，主要用在光纤通信上面。因为为了保持送给光模块的信号不是全1或者全0-A nice scrambler, mainly used in optical fiber communication above. Because in order to maintain the optical module of the signal is not sent to all 1 or all 0
Platform: | Size: 1024 | Author: 刘金华 | Hits:

[VHDL-FPGA-Verilog] scrambler-wimax

Description: This package contains synthesizable VHDL codes for scramber/descrambler module for IEEE 802.16 WiMAX PHY layer.
Platform: | Size: 1024 | Author: zpatel | Hits:

[Software Engineering] counter

Description: scrambler code for VHDL
Platform: | Size: 1024 | Author: amr tarek | Hits:

[VHDL-FPGA-Verilog] scramble

Description: 基于VHDL实现加扰器解扰器的设计，与仿真。-VHDL-based scrambler descrambler design and simulation.
Platform: | Size: 1891328 | Author: 杨超 | Hits:

[ELanguage] bin_count

Description: i m sending hdl code of dm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.-i m sending hdl code of ofdm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.
Platform: | Size: 28672 | Author: Nilesh panchal | Hits:

[VHDL-FPGA-Verilog] ParallelScrablerDescrambler

Description: VHDL code for parallel 6-bit scrambler and descrambler
Platform: | Size: 4096 | Author: maya333888 | Hits:

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