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[Other resource] some-usful-vhdl-source-code

Description: 一些实用的VHDL源码，有各种信号调制的，还有LCD控制的，出租车计价器等等源码。-some practical VHDL source code, a variety of signal modulation, there is the LCD control. taximeters, etc. source.
Platform: | Size: 1278750 | Author: 雨风 | Hits:

[VHDL-FPGA-Verilog] FFT的VHDL源代码

Description: FFT的VHDL源代码-fft vhdl source code
Platform: | Size: 29696 | Author: 阿林 | Hits:

[VHDL-FPGA-Verilog] vhdl实现alu的源代码

Description: VHDL实现ALU的源代码，并且提供了一个详细的testbench！-ALU VHDL source code, and provide a detailed testbench!
Platform: | Size: 1024 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] 100个vhdl设计例子

Description: 内附多路选择器，74系列芯片VHDL源码，加法器，FIR，比较器等大量例子，对初学VHDL语言很有好处。可用maxplus，quartus，synplicity等综合软件进行调试-contains multiple-choice, 74 chips VHDL source code, the adder, FIR, comparators, etc. are plenty of examples for beginners VHDL very good. Available maxplus, Quartus, synplicity integrated software debugging
Platform: | Size: 233472 | Author: 杰轩 | Hits:

[VHDL-FPGA-Verilog] VHDL3

Description: 这是一个自动售货机的vhdl源码，曾经是eda比赛的题目，供大家参考。-This is a vending machine in VHDL source code, the game had been sown topic, for your reference.
Platform: | Size: 534528 | Author: | Hits:

[source in ebook] some-usful-vhdl-source-code

Description: 一些实用的VHDL源码，有各种信号调制的，还有LCD控制的，出租车计价器等等源码。-some practical VHDL source code, a variety of signal modulation, there is the LCD control. taximeters, etc. source.
Platform: | Size: 1278976 | Author: 雨风 | Hits:

[Other] abcdefghijk

Description: 这是一个数字密码锁的VHDL源代码 花了很多时间才弄来的-This a digital code lock VHDL source code spent a lot of time obtained
Platform: | Size: 2048 | Author: 星星 | Hits:

[source in ebook] fftcode

Description: VHDL 的FFT 1024点源码。既有VHDL 的，也有Verlog的。比较好用。占用资源少-VHDL source code of the FFT 1024 points. Both VHDL and there are also some of the Verlog. Comparison of ease of use. Occupy less resources
Platform: | Size: 37888 | Author: 张加良 | Hits:

[VHDL-FPGA-Verilog] spi.tar

Description: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified.
Platform: | Size: 116736 | Author: hcjian | Hits:

[VHDL-FPGA-Verilog] ntsc_gen

Description: NTSC信号发生器VHDL源码。输出为BT656格式-NTSC signal generator VHDL source code. BT656 format output
Platform: | Size: 1024 | Author: 吕奔 | Hits:

[VHDL-FPGA-Verilog] hdlc

Description: HDLC通信模块发送接收模块VHDL源码-HDLC communication module to send receiver module VHDL source code
Platform: | Size: 3072 | Author: ditto | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: VHDL源代码程序，使用VHDL语言编写，一个FIFO的代码实现工程-VHDL source code, the use of VHDL language, a FIFO realize the code works
Platform: | Size: 3072 | Author: 罗兰 | Hits:

[VHDL-FPGA-Verilog] tdmddc_v71

Description: ddc的vhdl源代码，没有经过调试，只是作为分享，大家有什么意见和建议请回复邮件-ddc the VHDL source code, no debugging, just as share what everyone has opinions and suggestions, please reply to e-mail
Platform: | Size: 26624 | Author: zhangxi | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
Platform: | Size: 901120 | Author: 李帆 | Hits:

[VHDL-FPGA-Verilog] VHDLSourceCodeForADConvertersadv7123

Description: vhdl源码for模数转换器之七 vhdl源码for模数转换器之七-VHDL source code for the seven ADC ADC VHDL source code for the seven
Platform: | Size: 3072 | Author: rui | Hits:

[VHDL-FPGA-Verilog] VHDLSourceCodeForADConverterak4380

Description: 一个adc的vhdl源码之七 一个adc的vhdl源码之七(第一个压缩包含5个)-VHDL source code of a adc 71 adc of the VHDL source of the seven (the first compression contains 5)
Platform: | Size: 5120 | Author: rui | Hits:

[VHDL-FPGA-Verilog] SVPWM

Description: 这是一个对电机进行SVPWM调速控制的VHDL源代码程序,包括了rtl主程序和测试sim仿真程序-This is a motor SVPWM Speed VHDL source code control procedures, including the main program and test rtl simulation program sim
Platform: | Size: 13312 | Author: 杨国超 | Hits:

[VHDL-FPGA-Verilog] voterandcounter

Description: 用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
Platform: | Size: 2048 | Author: 韩笑 | Hits:

[Other] add4bit

Description: 一位全加器的VHDL源码与TEST BENCH.XILINX下通过-A full adder and the VHDL source code through TEST BENCH.XILINX
Platform: | Size: 813056 | Author: 祁才君 | Hits:

[VHDL-FPGA-Verilog] VHDL-source-code

Description: 一些有用的VHDL代码 包括伪随机序列发生器等-VHDL code, including some useful pseudo-random sequence generator, etc.
Platform: | Size: 45056 | Author: yfgf | Hits:
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