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[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码 DL : 0: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Update : 2025-02-17 Size : 416kb Publisher : ken
[VHDL-FPGA-Verilog] USB接口控制器参考设计_xilinx提供_vhdl DL : 0: USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code
Update : 2025-02-17 Size : 450kb Publisher : 陈旭
[VHDL-FPGA-Verilog] USB控制器VHDL程序 DL : 0: USB控制器VHDL程（usb_xilinx_vhdl）,用XILINX公司的FPGA实现-VHDL-USB controller (usb_xilinx_vhdl) XILINX FPGA
Update : 2025-02-17 Size : 59kb Publisher : 夏社
[Compress-Decompress algrithms] usb(FPGA) DL : 0: 基于FPGA的usb程序，采用VHDL语言编写。开发环境为ISE或者MAXPLUS2。-FPGA-based usb procedures, using VHDL language. Development Environment for the ISE or MAXPLUS2.
Update : 2025-02-17 Size : 137kb Publisher : 李浩
[VHDL-FPGA-Verilog] usb_xilinx_vhdl DL : 0: usb源码_xilinx_vhdl 这是Xilinx FPGA上的usb源码（VHDL)-usb-source _xilinx_vhdl This is a Xilinx FPGA on the usb source code (VHDL)
Update : 2025-02-17 Size : 55kb Publisher : nanotalk
[USB develop] usb DL : 0: 实现了USB接口。介绍了如何使用VERILOG语言实现USB的程序设计。-Realize the USB interface. Introduce how to use the Verilog language programming USB realize.
Update : 2025-02-17 Size : 137kb Publisher : xiexiao
[VHDL-FPGA-Verilog] usb DL : 0: 这是个USB 的VHDL 程序，进去直接双击ISE 就可以用了-This is a USB-VHDL procedures, into direct ISE can use double-click the
Update : 2025-02-17 Size : 1.57mb Publisher : 张亚伟
[USB develop] USB DL : 0: 这个工程是基于FPGA与Philips的D12 USbB 1.1的完整设计，包括VHDL驱动和主机应用程序及驱动-The project is based on FPGA and Philips of the D12 USbB 1.1 complete design, including VHDL-driven and mainframe applications and drivers
Update : 2025-02-17 Size : 2.62mb Publisher : Phirix Shaw
[USB develop] USB DL : 0: fpga设计的usb接口源程序，欢迎指导-FPGA design usb interface source code, welcomed the guidance of
Update : 2025-02-17 Size : 137kb Publisher : 陈楠
[VHDL-FPGA-Verilog] usb DL : 0: usb 硬件实现请大家多多指教-usb hardware realize the exhibitions please everyone
Update : 2025-02-17 Size : 2.19mb Publisher : qqq
[VHDL-FPGA-Verilog] USB DL : 0: USB源代码，基于VHDL语言编写，在QuartusII上面已验证其功能-USB source code, based on the VHDL language, verified in QuartusII above its function
Update : 2025-02-17 Size : 5kb Publisher : 周
[VHDL-FPGA-Verilog] USB DL : 0: 用VHDL实现的USB IP核，大家可以参考下-Use VHDL to achieve USB IP core, we can refer to the following
Update : 2025-02-17 Size : 1.09mb Publisher : 蔡飞
[USB develop] USB DL : 0: USB 设计（包括一个参考设计，和标准U盘）-USB design (including a reference design, and standards for U disk)
Update : 2025-02-17 Size : 534kb Publisher : zhangsan
[Driver Develop] USB DL : 0: usb的驱动开发、应用开发（c/c++),以及其FPGA固件开发（VHDL）。-usb driver development, application development (c/c++), as well as its FPGA firmware development (VHDL).
Update : 2025-02-17 Size : 137kb Publisher : zbs
[VHDL-FPGA-Verilog] USB DL : 0: USB通信协议的硬件描述语言代码，用于FPGA的总线接口控制器开发-USB communication protocol of the hardware description language code for the FPGA bus interface controller development
Update : 2025-02-17 Size : 137kb Publisher : shigengxin
[USB develop] usb DL : 0: USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.-USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
Update : 2025-02-17 Size : 6kb Publisher : polito
[Other] vhdl DL : 0: usb rtl code, to fpga or asic
Update : 2025-02-17 Size : 153kb Publisher : andy
[Other] vhdlshili DL : 0: 多个vhdl 实例，USB UART I2C VGA-vhdl USB UART I2C VGA
Update : 2025-02-17 Size : 467kb Publisher : 有
[VHDL-FPGA-Verilog] usb-blaster DL : 0: quartus多种USB-bletera 自制下载线！
Update : 2025-02-17 Size : 2.22mb Publisher : 陈长佳
[VHDL-FPGA-Verilog] USB DL : 0: USB的VHDL实现源码（使用VHDL硬件描述语言，通过Altera QuartusII 开发）-USB to achieve the VHDL source code (using VHDL hardware description language, through the development of Altera QuartusII)
Update : 2025-02-17 Size : 49kb Publisher : 刘磊

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