Search - VHDL-FPGA

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[Embeded-SCM Develop] FPGA的FFT源程序（VHDL） DL : 1: 采用 VHDL 语言编写 FPGA 上实现 FFT 源程序
Update : 2009-03-11 Size : 382.33kb Publisher : sun7784@126.com
[VHDL-FPGA-Verilog] VHDL的基本数学运算库 DL : 0: VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
Update : 2025-02-17 Size : 227kb Publisher :
[VHDL-FPGA-Verilog] Silicon_Integrity，VHDL DL : 0: 信号完整性，设计FPGA的基础-signal integrity, design based FPGA
Update : 2025-02-17 Size : 479kb Publisher :
[VHDL-FPGA-Verilog] fpga加密设计方法 DL : 0: FPGA加密的方法，对于那些需要加密自己的vhdl源代码的人来说，很有用-FPGA encryption methods for those who need to encrypt their VHDL source code in a way, very useful
Update : 2025-02-17 Size : 183kb Publisher : 陶伟炯
[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl DL : 0: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Update : 2025-02-17 Size : 758kb Publisher : 张涛
[VHDL-FPGA-Verilog] VHDL语言100例详解 DL : 0: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Update : 2025-02-17 Size : 6.33mb Publisher : 穆群生
[VHDL-FPGA-Verilog] 经典设计VHDL源代码 DL : 0: 非常好的VHDL小程序。内容齐全。基本的功能都有。-very good VHDL small programs. Content complete. The basic functions have.
Update : 2025-02-17 Size : 43kb Publisher : 林玉儿
[VHDL-FPGA-Verilog] VHDL的编程实例 DL : 0: 别人的一些常用的VHDL源代码,希望对各位有用!-some others used the VHDL source code, and I hope to you and useful!
Update : 2025-02-17 Size : 165kb Publisher : 大大头
[VHDL-FPGA-Verilog] VHDL 的实例程序，共44个 DL : 0: 经典VHDL 的实例程序，共44个！要下载的尽快-classic examples of VHDL, with a total of 44! To download as soon as possible
Update : 2025-02-17 Size : 42kb Publisher : 立立
[DSP program] 基于FPGA的数字信号显示系统软硬件设计 DL : 0: 该文阐述了现场可编程逻辑器件FPGA的主要特点，应用FPGA芯片和VHDL硬件描述语言设计的模拟示波器数字信号显示系统的设计原理和设计方法。-this paper, the field programmable logic devices FPGA main feature FPGA chip and VHDL hardware description language design analog signals to digital oscilloscope system design principles Design and Methods.
Update : 2025-02-17 Size : 429kb Publisher : 张志华
[Static control] ipcore51 DL : 0: 51核，用VHDL编写，通过FPGA验证-51 nuclear, prepared with VHDL, FPGA verification
Update : 2025-02-17 Size : 955kb Publisher : 汪平
[Other] fpga-jpeg DL : 0: vhdl实现的ＪＰＥＧ嘿嘿嘿嘿圆圆嘿嘿另-VHDL achieve JPEG laughter laughter another round laughter
Update : 2025-02-17 Size : 101kb Publisher : window
[Books] vhdl-fpga DL : 0: 这是一本很好用的VHDL编程书，各位看了就明白。-This is a very good use of VHDL programming, you read it to understand.
Update : 2025-02-17 Size : 7.37mb Publisher : lqt76
[VHDL-FPGA-Verilog] FPGA_SUM99_VHDL_SOURCE DL : 0: 基于FPGA的直接数字合成器的设计与分析的代码程序,代码格式为VHDL-FPGA-based Direct Digital Synthesis Design and Analysis of the code procedures for VHDL code format
Update : 2025-02-17 Size : 5kb Publisher : 莫汉伟
[Documents] UART(FPGA) DL : 0: 基于FPGA的串行通信UART控制器，采用VHDL语言编写，包含多个子模块。在ISE或FPGA的其它开发环境下新建一个工程，然后将文档中的各个模块程序添加进去，即可运行仿真。源程序已经过本人的仿真验证。-FPGA-based UART serial communication controller, using VHDL language, includes a number of sub-module. ISE FPGA or in the other developing a new environment, then documentation of the various modules of procedures added to it, will be running simulation. I have been the source of the simulation.
Update : 2025-02-17 Size : 14kb Publisher : 李浩
[Compress-Decompress algrithms] usb(FPGA) DL : 0: 基于FPGA的usb程序，采用VHDL语言编写。开发环境为ISE或者MAXPLUS2。-FPGA-based usb procedures, using VHDL language. Development Environment for the ISE or MAXPLUS2.
Update : 2025-02-17 Size : 137kb Publisher : 李浩
[Other] VHDL-FPGA-clock DL : 1: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Update : 2025-02-17 Size : 263kb Publisher : 王越
[VHDL-FPGA-Verilog] FPGA-based_oscilloscope DL : 0: FPGA-based_oscilloscope,VHDL写的实现示波器的程序，及完整的工程描述文档-FPGA-based_oscilloscope. VHDL was oscilloscope to achieve the realization of the process, and complete the project description document
Update : 2025-02-17 Size : 223kb Publisher : 严刚
[VHDL-FPGA-Verilog] VHDL-vga_core(vhdl) DL : 0: VHDL-vga_core(vhdl).rar FPGA上实现 VGA的IP（VHDL）-VHDL-vga_core (vhdl). RarFPGA realize VGA on the IP (VHDL)
Update : 2025-02-17 Size : 448kb Publisher : nanotalk
[Other] ref-sdr-sdram-vhdl DL : 0: FPGA连接SDRAM的源程序，VHDL语言实现，功能基本完全。应用效果好。-FPGA connected SDRAM source, VHDL language, the basic function fully. Application effective.
Update : 2025-02-17 Size : 715kb Publisher : young

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