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[VHDL-FPGA-Verilog] whole

Description: ov7620的CPLD采集程序，VHDL语言-ov7620 CPLD acquisition procedures, VHDL
Platform: | Size: 1024 | Author: 韦新峰 | Hits:

[VHDL-FPGA-Verilog] VHDL的基本数学运算库

Description: VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
Platform: | Size: 232448 | Author: | Hits:

[VHDL-FPGA-Verilog] 交通灯实验报告

Description: vhdl交通灯实验报告-VHDL traffic lights Experimental Report
Platform: | Size: 100352 | Author: 哈哈 | Hits:

[Other] FFT16

Description: 基于FPGA的16点FFT快速傅立叶变换的Verilog源代码。-the FFT implement of Verilog based on FPGA
Platform: | Size: 2048 | Author: lsd | Hits:

[VHDL-FPGA-Verilog] VGA显示的FPGA实现方法

Description: VGA显示的FPGA实现方法，包括原理和一个小例子。-the application of VGA display with FPGA,include theory and example
Platform: | Size: 84992 | Author: 王天权 | Hits:

[VHDL-FPGA-Verilog] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6633472 | Author: 穆群生 | Hits:

[VHDL-FPGA-Verilog] VHDL的编程实例

Description: 别人的一些常用的VHDL源代码,希望对各位有用!-some others used the VHDL source code, and I hope to you and useful!
Platform: | Size: 168960 | Author: 大大头 | Hits:

[VHDL-FPGA-Verilog] VHDL 的实例程序，共44个

Description: 经典VHDL 的实例程序，共44个！要下载的尽快-classic examples of VHDL, with a total of 44! To download as soon as possible
Platform: | Size: 43008 | Author: 立立 | Hits:

[VHDL-FPGA-Verilog] codeofvhdl2006

Description: 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】 - [ Classics design ] the VHDL source code downloads ~ ~ classics the design to include: [ Vending machine ], [ electron clock ], [ traffic light traffic signal system ], [ step of 杩涚數 machine localization control system ], [ direct current machine speed control system ], [ calculator ], [ array LED display control system ] the basic numeral logical design includes: [ Latch ], [ multichannel selector ], [ 涓夋
Platform: | Size: 44032 | Author: senkong | Hits:

[Post-TeleCom sofeware systems] rs232_send

Description: rs232 vhdl程序 可以实行异步串行通信,这里只有send-rs232 vhdl procedures implemented asynchronous serial communication, here only send
Platform: | Size: 1024 | Author: 李湘宏 | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] wp_max_flash

Description: FPGA中FLASH配置控制源码,VHDL和Verilog-FPGA source code in the FLASH configuration control, VHDL and Verilog
Platform: | Size: 37888 | Author: wanggui | Hits:

[VHDL-FPGA-Verilog] fpga-jpeg

Description: jepg verilog example
Platform: | Size: 103424 | Author: 展望 | Hits:

[VHDL-FPGA-Verilog] FPGA-SD-COMMUNICATION

Description: 基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL-QUARTUSII software implementation based on FPGA (ATERA CYCLONE II series) with SD Card SD mode digital communication language verilog HDL
Platform: | Size: 5064704 | Author: chenbinjie | Hits:

[VHDL-FPGA-Verilog] AD9229-FPGA-files

Description: adi串行AD AD9229的控制使用ISE平台 Verilog语言 -adi serial ADAD9229 control the use of ISE platform Verilog language
Platform: | Size: 184320 | Author: 徐凯 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 组成原理的大作业，写一个计算器，用verilog语言写的-The composition of the major principles of operation, write a calculator, using the language written in Verilog
Platform: | Size: 8943616 | Author: 陈江 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 采用VHDL语言设计一个4通道的数据采集控制模块。系统的功能描述如下： 1.系统主时钟为100 MHz。 2.数据为16位-数据线上连续2次00FF后数据传输开始。 3.系统内部总线宽度为8位。 4.共有4个通道（ch1、ch2、ch3、ch4），每个通道配备100 Bytes的RAM，当存满数据后停止数据采集并且相应通道的状态位产生报警信号。 5.数据分为8位串行输出，输出时钟由外部数据读取电路给出。 6.具备显示模块驱动功能。由SEL信号设置显示的通道，DISPLAY信号启动所选通道RAM中数值的显示过程。数值顺次显示一遍后显示结束，可以重新设定SEL的值选择下一个通道。模块数据线为8位，显示器件为4个8段LED。 7.数据采集模式如下：单通道采集（由SEL信号选择通道），多通道顺次采集（当前通道采满后转入下一通道），多通道并行采集（每通道依次采集一个数据）。模式由控制信号MODE选择，采集数据的总个数由NUM_COLLECT给出。 8.数据采集过程中不能读取，数据读取过程中不能采集-err
Platform: | Size: 5782528 | Author: pengfu | Hits:

[Compress-Decompress algrithms] Huffmann-Coding-FPGA

Description: huffman coding in vhdl or verilog with explanation
Platform: | Size: 479232 | Author: sandeep | Hits:

[VHDL-FPGA-Verilog] Verilog-hdlFPGA

Description: 关于FPGA的提高篇，Verilog HDL语言写的， 包含LCD控制VHDL程序与仿真，AD/DA，MASK，FSK，PSK，正弦波发生器，等等经典程序-Articles on improving the FPGA, Verilog HDL language, and includes LCD control procedures and VHDL simulation, AD/DA, MASK, FSK, PSK, sine wave generator, and so the classic procedure
Platform: | Size: 1181696 | Author: chenfeihu | Hits:

[VHDL-FPGA-Verilog] The Complete Verilog Book (Vivek Sagdeo)

Description: programming book verilog
Platform: | Size: 5337088 | Author: mani1 | Hits:
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