Search - VIRTEXII

[Software Engineering] XUPV2P_User_Guide

Description: XUPV2P User Guide VirtexII Pro-XUPV2P VirtexII Pro User Guide
Platform: | Size: 1855440 | Author: 沈佳麒 | Hits:

[Software Engineering] XUPV2P_User_Guide

Description: XUPV2P User Guide VirtexII Pro-XUPV2P VirtexII Pro User Guide
Platform: | Size: 1855488 | Author: 沈佳麒 | Hits:

[VHDL-FPGA-Verilog] BIST_Circuits

Description: BIST 电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-BIST circuits IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 5120 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: Xilinx可编程逻辑器件的高级应用与设计技巧全面介绍Xilinx的CoolRunnerII Spartan-3 Virtex-II VirtexII pro等器件的结构特性，以及ISE6及其辅助设计工具。 -Xilinx programmable logic devices and design techniques for advanced applications a comprehensive introduction to Xilinx s CoolRunnerII Spartan-3 Virtex-II VirtexII pro, such as the structural characteristics of the device, as well as its ISE6-aided design tools.
Platform: | Size: 41021440 | Author: 胡赟星 | Hits:

[Windows Develop] slideshow_256mb

Description: XUP VirtexII Pro Development board Slideshow_256mb-XUP VirtexII Pro Development board Slideshow_256mb
Platform: | Size: 3040256 | Author: ioannis | Hits:

[VHDL-FPGA-Verilog] bist

Description: design for test Test and Design-for-Test for memory bist-design for test
Platform: | Size: 1435648 | Author: sky | Hits:

[VHDL-FPGA-Verilog] new_bord_TX_10bitX2_2_5G

Description: Xilinx VirtexII-pro 的开发板工程文件，它是在ISE开发环境中实现的。连接有RAM、串口、LED灯、Camera-link接口等，实现的从工业相机到光缆的转换。-xilinx virtex2-pro project,camera-link
Platform: | Size: 3675136 | Author: 姓名 | Hits:

[Program doc] Xilinx VirtexII datasheet

Description: Xilinx VirtexII datasheet
Platform: | Size: 1889696 | Author: xymzzz@aliyun.com.cn | Hits:

[Goverment application] Built_in_Demo_rev_1_1

Description: FPGA virtexii pro音频设计实例，很好用，真的雷奥，，，，，，，，真的真的
Platform: | Size: 29455360 | Author: leo | Hits:

[VHDL-FPGA-Verilog] cachecontroller_latest.tar

Description: This project is to develop a direct mapped cache controller for embedded applications. Key Design Features - Direct mapped with configurable address size, line size and number of cache lines - Non Pipelined architecture - No Cache flush Synthesis will be conducted using VirtexII Pro
Platform: | Size: 122880 | Author: weijie | Hits:

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[Software Engineering] XUPV2P_User_Guide

[Software Engineering] XUPV2P_User_Guide

[VHDL-FPGA-Verilog] BIST_Circuits

[VHDL-FPGA-Verilog] Xilinx

[Windows Develop] slideshow_256mb

[VHDL-FPGA-Verilog] bist

[VHDL-FPGA-Verilog] new_bord_TX_10bitX2_2_5G

[Program doc] Xilinx VirtexII datasheet

[Goverment application] Built_in_Demo_rev_1_1

[VHDL-FPGA-Verilog] cachecontroller_latest.tar

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