Search - Verilog HELLO

[VHDL-FPGA-Verilog] hello_flash

Description: hello_flash是ALTERA的NIOSII核的标准程序。读写FPGA外带的Flash。-ALTERA the hello_flash is standard procedure for nuclear NIOSII. Hit-and-run of the FPGA to read and write Flash.
Platform: | Size: 1024 | Author: 王祥以 | Hits:

[Software Engineering] part6

Description: run hello on 7-segments led on de2 board using verilog
Platform: | Size: 587776 | Author: atula136 | Hits:

[VHDL-FPGA-Verilog] displayHELLO

Description: verilog语言编写，在altera公司的de2实验板上实现八个数码管循环显示HELLO-verilog language, in the experimental altera de2 board to achieve the company' s eight digital control loop shown HELLO
Platform: | Size: 2048 | Author: luping | Hits:

[VHDL-FPGA-Verilog] lock-and-lcd

Description: 基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言，分为按键输入模块、LED指示灯模块及LCD显示模块，采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配，由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时，LCD显示“HELLO! WELCOME!Enter the code:当”，密码输入正确时，LED灯D7亮，同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”，当密码输入错误时，LED灯D8亮，并在LCD显示屏上显示字符串“NO!!You stupid!!you are worry!!!”其中，LCD显示作为本次设计的核心内容，字符型LCD通常有14条引脚线或16条引脚线的LCD，多出来的2条线是背光电源线VCC(15脚)和地线GND(16脚)，其控制原理与14脚的LCD完全一样-Base YuBo gen experiment box UP- FPGA2C35- Ⅱ and director- Verilog HDL hardware description language, divided into key input module, the LED indicator light module and LCD display module, the BTN1, BTN2 buttons as input the input password and set in four matches, the password by D1, D2 and D3, D4 four lamp that LED lamp to indicate input password of digits. Boot, LCD display "HELLO!!!!!!!!!! The code: backgound Enter when", a password when right, LED lamp, while D7 light displayed on the LCD screen experiment box string "Good!! Well done! You right!!!" hero When a password mistake, LED lamp light, and in D8 displayed on the LCD screen "NO!! You string can be hindered stupid!!!!!!!!!!!!!!!!!" hero Among them, LCD display as the core content of the design, character type LCD usually has 14 pin line or 16 pins line of LCD, extra 2 line is backlit cord VCC (15 feet) and landlines GND (16 feet), the control principle and 14 feet LCD exactly the same
Platform: | Size: 3072 | Author: 吴寿武 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: a dvan let go look ing down hello how are you today
Platform: | Size: 5048320 | Author: nghia | Hits:

[VHDL-FPGA-Verilog] System_Demons

Description: 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。 5.构造函数带参数的例子。 6.轮转仲裁的例子。 7.使用类摸板的例子。 8.如何在模块中包含子模块。 9.SystemC的Transaction级验证示例。 10.如何trace一个数组 11.SystemC中使用测试向量文件输入的例子。 12.SystemC采用UDP/TCP通信的例子。 13.Cadence的ncsc的例子。 -0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Platform: | Size: 532480 | Author: sdd | Hits:

[VHDL-FPGA-Verilog] zidong_led_water

Description: 用Verilog语言实现了将50MHz时钟分频到1Hz，实现了自动流水显示HELLO字母功能-Verilog language of the 50MHz clock frequency to 1Hz, realized the function of automatic water display HELLO letters
Platform: | Size: 320512 | Author: 黄刚 | Hits:

[Software Engineering] TOOGLED-SCROLL

Description: This verilog pogram to toggle the scrolling of hello world on seven segment display of BASYS2 board using pushbutton. -This is verilog pogram to toggle the scrolling of hello world on seven segment display of BASYS2 board using pushbutton.
Platform: | Size: 2048 | Author: Vishakha | Hits:

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[VHDL-FPGA-Verilog] hello_flash

[Software Engineering] part6

[VHDL-FPGA-Verilog] displayHELLO

[VHDL-FPGA-Verilog] lock-and-lcd

[VHDL-FPGA-Verilog] Verilog-HDL

[VHDL-FPGA-Verilog] System_Demons

[VHDL-FPGA-Verilog] zidong_led_water

[Software Engineering] TOOGLED-SCROLL

[Embeded-SCM Develop] bracket

[VHDL-FPGA-Verilog] Helloworld

[Embeded-SCM Develop] oc8051内核程序

[Documents] 《HELLO FPGA》-项目进阶篇v2.0

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