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[Special Effects] FPGA_for_I2C

Description: i2c code for the verilog -i2c code for the Verilog
Platform: | Size: 214016 | Author: zhang chi | Hits:

[Compress-Decompress algrithms] i2c(FPGA)

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
Platform: | Size: 212992 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] cmos_FPGA

Description: 采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来-Verilog language, to achieve control of the FPGA chip video data acquisition, Data will be stored up by frame
Platform: | Size: 1024 | Author: margie | Hits:

[Software Engineering] FPGA_GPS_C_A

Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.
Platform: | Size: 163840 | Author: xiaozhu | Hits:

[VHDL-FPGA-Verilog] key

Description: 一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
Platform: | Size: 199680 | Author: 林虎 | Hits:

[VHDL-FPGA-Verilog] uartverlog

Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[VHDL-FPGA-Verilog] wp_max_flash

Description: FPGA中FLASH配置控制源码,VHDL和Verilog-FPGA source code in the FLASH configuration control, VHDL and Verilog
Platform: | Size: 37888 | Author: wanggui | Hits:

[Other Embeded program] AD7865test1

Description: verilog hdl写的利用fpga控制ad7865进行多路ad数据采集的程序源代码。-err
Platform: | Size: 309248 | Author: nwpu2005 | Hits:

[Com Port] RS232

Description: FPGA实现RS-232串口收发的Verilog程序，已经调通。-FPGA realization of RS-232 serial port to send and receive the Verilog procedures, Qualcomm has been transferred.
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] jtag

Description: verilog 实现的 jtag TAP ， 转自 opencore.com， 已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 635904 | Author: hegs | Hits:

[VHDL-FPGA-Verilog] scrambler

Description: 通信系统中的加扰与解扰程序，用verilog语言实现，有波形文件可以直接查看功能-Communication Systems scrambling and descrambling process, with Verilog language, has waveform files can be directly read features
Platform: | Size: 323584 | Author: 桃子 | Hits:

[VHDL-FPGA-Verilog] ac97_verilog_sourcecode

Description: AC97芯片的verilog实现，有兴趣可以研究下。verilog是一种硬件开发语言，语法与c类似。与VHDL并列为IC开发两大编程语言-AC97 chip Verilog realize, who are interested can study. Verilog is a hardware development language, grammar and c similar. IC with VHDL as a programming language to develop two
Platform: | Size: 124928 | Author: 小步 | Hits:

[VHDL-FPGA-Verilog] liangzhu

Description: FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用，验证通过，工程环境为Altera Quartus II -Introduction to the Verilog HDL FPGA development process 2 --- Butterfly music player, the real available, verified by the project environment for the Altera Quartus II
Platform: | Size: 301056 | Author: renyong0801 | Hits:

[VHDL-FPGA-Verilog] ISP1362

Description: Verilog 编写的ISP1362的控制器IP核，altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
Platform: | Size: 18432 | Author: zhyy | Hits:

[VHDL-FPGA-Verilog] zigzag

Description: 用于FPGA的Z变化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-脫脙脫脷FPGA渭脛Z 卤 盲 禄炉 脣茫 篓 渭脛HDL 卤 脿脗毛 拢 卢 掳 眉脌 篓 VHDL 录 掳 Verilog
Platform: | Size: 7168 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] pro035

Description: verilog 编写基于SRAM(CY7C1041)的代码-Verilog prepared based on the SRAM (CY7C1041) code
Platform: | Size: 888832 | Author: wb | Hits:

[VHDL-FPGA-Verilog] usb_FPGA

Description: 实现USB接口功能的VHDL和verilog完整源代码-Implementation USB interface functions of the VHDL and Verilog source code integrity
Platform: | Size: 260096 | Author: liang | Hits:

[VHDL-FPGA-Verilog] ram_Test

Description: RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
Platform: | Size: 3072 | Author: 王欢 | Hits:

[VHDL-FPGA-Verilog] FPGA_SDRAM_PCI

Description: 一个基于FPGA的PCI数据采集程序，包括SDRAM控制，PCI9054时序控制，开发语言verilog，开发环境quartus-FPGA-based PCI data acquisition procedures, including SDRAM control, PCI9054 timing control, the development of language verilog, development environment quartusII
Platform: | Size: 2798592 | Author: 李国扬 | Hits:

[Embeded-SCM Develop] verilog_FPGA_DDC

Description: 这是一个用verilog HDL实现的实现数字下变频的源代码。-This is a verilog HDL used to achieve the realization of digital down conversion of the source code.
Platform: | Size: 2790400 | Author: 王坤 | Hits:
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