Search - Verilog R

[Other resource] ImplementationFromAlgorithmDesigntoHardwareLogic.r

Description: 第一章数字信号处理、计算、程序、算法和硬线逻辑的基本概念第二章 Verilog HDL设计方法概述第三章 Verilog HDL的基本语法第四章不同抽象级别的Verilog HDL模型第五章基本运算逻辑和它们的Verilog HDL模型第六章运算和数据流动控制逻辑-the first chapter of digital signal processing and computing procedures, hard-line algorithm and the basic logic of the concept of the second chapter of Verilog HDL design methods outlined in the third chapter Verilo g HDL basic grammar Chapter 4 different levels of abstract Verilog HDL model V basic arithmetic logic and their Verilog HDL model of the sixth chapter operations and data flow control logic
Platform: | Size: 422091 | Author: 陈亨利 | Hits:

[Other resource] Digital-Design-and-Computer-Architecture-verilog.r

Description: 《数字设计和计算机体系结构》一书MIPS verilog源码。
Platform: | Size: 3473 | Author: guo | Hits:

[SCM] oc8051

Description: 51的VERILOG代码！适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
Platform: | Size: 1220608 | Author: 林建加 | Hits:

[MiddleWare] oaVerilog

Description: openaccess与verilog互相转化时所用的源代码，在安装了openaccess的windows和linux上都可以使用。-openaccess with Verilog into each other when used in the source code, the installation of the windows and openaccess on Linux can use.
Platform: | Size: 334848 | Author: 望雁峰 | Hits:

[Other] ImplementationFromAlgorithmDesigntoHardwareLogic.r

Description: 第一章数字信号处理、计算、程序、算法和硬线逻辑的基本概念第二章 Verilog HDL设计方法概述第三章 Verilog HDL的基本语法第四章不同抽象级别的Verilog HDL模型第五章基本运算逻辑和它们的Verilog HDL模型第六章运算和数据流动控制逻辑-the first chapter of digital signal processing and computing procedures, hard-line algorithm and the basic logic of the concept of the second chapter of Verilog HDL design methods outlined in the third chapter Verilo g HDL basic grammar Chapter 4 different levels of abstract Verilog HDL model V basic arithmetic logic and their Verilog HDL model of the sixth chapter operations and data flow control logic
Platform: | Size: 421888 | Author: 陈亨利 | Hits:

[VHDL-FPGA-Verilog] jtag

Description: verilog 实现的 jtag TAP ，转自 opencore.com，已通过验证-Verilog realize the jtag TAP, carried opencore.com, has passed validation
Platform: | Size: 635904 | Author: hegs | Hits:

[ARM-PowerPC-ColdFire-MIPS] Digital-Design-and-Computer-Architecture-verilog.r

Description: 《数字设计和计算机体系结构》一书MIPS verilog源码。
Platform: | Size: 3072 | Author: guo | Hits:

[Other] AnalogBehavioralModelingWithTheVerilog-ALanguage.r

Description: 模拟电路设计软件仿真语言和数字语言VERILOG想对应主要用于模拟系统建模-Analog circuit design software and digital simulation language VERILOG would like to correspond to the main language used to simulate the system modeling
Platform: | Size: 5714944 | Author: 赵晓迪 | Hits:

[VHDL-FPGA-Verilog] RGBtoYCbCr

Description: 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件. -FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
Platform: | Size: 411648 | Author: Jackson | Hits:

[VHDL-FPGA-Verilog] jiaotongdeng

Description: 1). 用红、绿、黄三色发光二极管作信号灯。主干道为东西向，有红、绿、黄三个灯；支干道为南北向，也有红、绿、黄三个灯。红灯亮禁止通行；绿灯亮允许通行；黄灯亮则给行驶中的车辆有时间停靠到禁行线之外。 2).由于主干道车辆较多而支干道车辆较少，所以主干道绿灯时间较长。当主干道允许通行亮绿灯时，支干道亮红灯。而支干道允许通行亮绿灯时，主干道亮红灯，两者交替重复。主干道每次放行50秒，支干道每次放行30秒。在每次由亮绿灯变成亮红灯的转换过程中间，需要亮5秒的黄灯作为过渡，以使行驶中的车辆有时间停靠到禁行线以外。 3). 能实现正常的、即时显示功能。用DE2上的四个七段数码管作为倒计时显示器。分别显示东西、南北方向的红灯、绿灯、黄灯时间。 4).能实现特殊状态的功能显示。设S为特殊状态的传感器信号，当Ｓ=1时，进入特殊状态。当Ｓ=0时，退出特殊状态。按S后，能实现特殊状态功能：（1）显示器闪烁；（2）计数器停止计数并保持在原来的数据；（3）东西、南北路口均显示红灯状态；（4）特殊状态结束后，能继续对时间进行计数。 5).能实现总体清零功能。按下R后，系统实现总清零，计数器由初始状态开始计数，对应状态的指示灯亮。 -1). With red, green, yellow three-color light-emitting diodes for lights. For the east-west trunk road, has red, green, yellow three lights support for the north-south trunk road, there are red, green, yellow three lights. Red light curfew green permit passage yellow light is to the moving vehicles have the time of call to cut outside the lane. 2). Because of the trunk road vehicles more vehicles and less trunk extension, so a longer green time of a main road. When the main road access permit a green light when the trunk road red sticks. Permit access roads and support a green light when the trunk road red, the two alternating repetition. Allowed 50 seconds for each trunk, branch trunk release each 30 seconds. At each green light into red by the conversion process between the need for five seconds of yellow light as a transitional measure to enable the moving vehicles have the time of call to ban outside lane. 3). To achieve a normal, real-time display. Using DE2 four seventh
Platform: | Size: 2048 | Author: 靓仔 | Hits:

[Other] Verilog

Description: verilog的简要教程基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

[Communication-Mobile] spi_burst

Description: Verilog block SPI for Burst R/W Operation
Platform: | Size: 5120 | Author: 苗淼 | Hits:

[matlab] wierlesscommunicationfpgadesignmatlabverilogcode.r

Description: 无线通信FPGA设计的所有源码，具有良好的使用价值-verilog matlab ISE
Platform: | Size: 214016 | Author: 吕鑫宇 | Hits:

[VHDL-FPGA-Verilog] xapp283

Description: YUV到RGB的色彩空间转换器(VHDL,Verilog and doc)-Color Space Converter: Y’CrCb to R’G’B’
Platform: | Size: 175104 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] rom

Description: 基于Verilog语言编写的各种只读存储器rom和随机存储器ram-Verilog language based on a variety of read-only memory rom and random access memory ram
Platform: | Size: 704512 | Author: 李辽原 | Hits:

[VHDL-FPGA-Verilog] SystemVerilogEventRegionsRaceAvoidanceGuidelines.r

Description: The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This paper details common Verilog verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in- depth explanation of SystemVerilog event regions is included to help understand how race- reduction goals have been met. Important design & testbench coding guidelines are also included.-The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This paper details common Verilog verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in- depth explanation of SystemVerilog event regions is included to help understand how race- reduction goals have been met. Important design & testbench coding guidelines are also included.
Platform: | Size: 356352 | Author: 陈斌 | Hits:

[Other] Fromalgorithmdesigntohardwarelogicimplementation.r

Description: 《从算法设计到硬件逻辑的实现》（夏宇闻编写）实验练习和Verilog语法手册-" From algorithm design to hardware implementation of logic" (Xia Yu Wen prepared) laboratory exercises, and Verilog syntax manual
Platform: | Size: 2374656 | Author: 苗伟 | Hits:

[Other] verilog_RAM

Description: verilog 实现的一个双口RAM及其控制模块.我通过先存入64个数据在读出仿真通过。-verilog implementation of a dual-port RAM.
Platform: | Size: 1024 | Author: 世海 | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
Platform: | Size: 290816 | Author: 阿虎 | Hits:

[VHDL-FPGA-Verilog] ahdl--sine-wave-code-with-rom-look-up-table_imp.r

Description: hi this an verilog codes-hi this is an verilog codes
Platform: | Size: 8192 | Author: praha | Hits:

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