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[VHDL-FPGA-Verilog] DDR（双速率）SDRAM控制器参考设计verilog代码

Description: DDR SDRAM reference design documentation
Platform: | Size: 895281 | Author: tony_gx@hotmail.com | Hits:

[Embeded-SCM Develop] ref-ddr-sdram-verilog

Description: sdram的verilog的源码实现-sdram verilog source code realizes
Platform: | Size: 904192 | Author: zfhustb | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx
Platform: | Size: 131072 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[VHDL-FPGA-Verilog] very-good-ok-ref-ddr-sdram-verilog

Description: Sdr SDRAM控制器参考设计,很好的-Sdr SDRAM controller reference design, very good
Platform: | Size: 894976 | Author: 姚明 | Hits:

[MPI] ddr_sdr_V1_1

Description: ddr verilog代码,实现DDR内存控制，是一个高效率的程序-ddr verilog code, realize DDR memory control, is a highly efficient procedure
Platform: | Size: 38912 | Author: | Hits:

[Software Engineering] DDR_SDRAM_controller_verilog

Description: DDR SRAM控制器的verilog完整设计文档（包含有完整的verilog源代码），-DDR SRAM controller complete Verilog design documents (including a complete Verilog source code),
Platform: | Size: 475136 | Author: lipengfei | Hits:

[Other] 128Mb_ddr

Description: 128Mb DDR verilog源程序-128Mb DDR verilog source code
Platform: | Size: 23552 | Author: tiantian | Hits:

[VHDL-FPGA-Verilog] sdram32

Description: DDR SDRAM source verilog source codes
Platform: | Size: 25600 | Author: sachin | Hits:

[Other] rtl

Description: ddr controller in verilog-ddr controller in verilog...............
Platform: | Size: 69632 | Author: guanchuanjian | Hits:

[VHDL-FPGA-Verilog] ddr-sdram--chengxu

Description: ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
Platform: | Size: 14336 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] ddrsdram_verilog

Description: 内附doc是DDR SDRAM 参考设计文档；model包含SDRAM Verilog的模型；simulation包含verilog测试平台、modelsim工程文、设计库函数；source包含verilog源文件；synthesis包含工程的综合文件 。-Enclosing the doc is a DDR SDRAM reference design documentation model contains SDRAM Verilog model simulation with verilog test platform, modelsim project text, design library function source contains the verilog source files synthesis comprehensive document that contains the project.
Platform: | Size: 751616 | Author: 陈少华 | Hits:

[VHDL-FPGA-Verilog] ddr-sdram

Description: DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.
Platform: | Size: 923648 | Author: runxin | Hits:

[VHDL-FPGA-Verilog] doc17414x90

Description: ddr设计控制器，源代码！Verilog代码！-设计控制器，源代码！Verilog代码！
Platform: | Size: 646144 | Author: 张杰 | Hits:

[Other] ddr-sdram-verilog-resource

Description: 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-description the resource code of ddr_sram
Platform: | Size: 896000 | Author: wangyuzhuo | Hits:

[Software Engineering] DDRcontroller

Description: 对DDR控制器的FPGA实现及其代码和参考注释-verilog source code written to read and write DDR
Platform: | Size: 800768 | Author: 张琦 | Hits:

[VHDL-FPGA-Verilog] ref-ddr-sdram-verilog

Description: ddr_sdram开发参考verilog建模-ddr_sdram with verilog
Platform: | Size: 753664 | Author: pengyong | Hits:

[VHDL-FPGA-Verilog] Altera_DDR_controller_core

Description: Altera DDR SDRAM控制器完整Verilog代码包，包括Verilog源代码，Doc说明文档，仿真DDR芯片模型，仿真testbench等-Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Platform: | Size: 752640 | Author: 沈志 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 基于FPGA的ddr控制器的设计与实现，verilog，ISE-FPGA-based controller design and implementation of ddr, verilog, ISE
Platform: | Size: 179200 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 利用硬件verilog语言实现DDR2功能，对信息快速存储-VERILOG DDR2
Platform: | Size: 316416 | Author: | Hits:
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