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Description: 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
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Size: 386048 |
Author: 杨艺 |
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Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
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Size: 133120 |
Author: yuanfeng |
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Description: 一个关于声音处理的Verilog语言编写的解码芯片,可以用于FPGA处理芯片的IP核,欢迎大家来用。-a voice on the Verilog language decoder chip, FPGA can be used to handle IP core chips, all are welcome to use.
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Size: 2048 |
Author: 赵春生 |
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Description: jpeg解码电路,是verilog编写的,可以综合,很有实用价值。-jpeg decoder circuit, is prepared verilog, synthesis, very practical value.
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Size: 181248 |
Author: blueli |
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Description: viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
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Size: 44032 |
Author: 林四昆 |
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Description: 介绍了viterbi译码器的编解码器的设计,包括decoder.v,encoder.v.control.v,ram.v等,压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
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Size: 62464 |
Author: yaoyongshi |
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Description: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
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Size: 9216 |
Author: wangyunshann |
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Description: <Verilog HDL 语言编程》
RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
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Size: 11264 |
Author: 李映波 |
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Description: 很多实用的例程,包括触发器,译码器,多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX
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Size: 113664 |
Author: 张席龙 |
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Description: cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program
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Size: 13312 |
Author: 陈臣 |
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Description: 用verilog编写的bch译码器,包括测试文件,随机加载了比特流,进行了测试。-Prepared using Verilog BCH decoder, including test papers, random load the bit stream to carry out the test.
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Size: 357376 |
Author: 牛顿 |
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Description: h.264(verilog HDL)
这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
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Size: 99328 |
Author: 陈成 |
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Description: 一个verilog源代码,用于译码器的编程。-A verilog source code, for programming decoder.
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Size: 65536 |
Author: PUDN_CHEN |
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Description: Verilog HDL 实现的JPEG200的MQ解码-JPEG2000 MQ DECODER BASED ON FPGA, Verilog HDL
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Size: 1518592 |
Author: 林木 |
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Description: verilog程序,实现了(2,1,4)卷积码编码,和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
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Size: 3072 |
Author: xiongherui |
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Description: The mp3 decoder write by using Verilog
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Size: 2150400 |
Author: hqgoldswan |
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Description: decoder verilog. it is a 3 t0 5 decoder that compile with modelsim.
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Size: 1024 |
Author: MohammadReza |
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Description: Viterbi译码器的编解码器的设计
用Verilog实现-Viterbi decoder。Verilog
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Size: 64512 |
Author: 李风飞 |
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Description: 指令译码器的设计vhdl语言或者verilog HDL语言对单片机程序的处理-Instruction decoder design vhdl language or verilog HDL language processing microcomputer programs
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Size: 1024 |
Author: wvqyd |
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Description: ldpc decoder 802-3an,最新版本,verilog版本.完成基于LDPC解码 -ldpc decoder 802-3an, the latest version, verilog version. LDPC decoder based on the completion
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Size: 884736 |
Author: shen |
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