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[Software Engineering] FPGA_GPS_C_A

Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。
Platform: | Size: 164313 | Author: xiaozhu | Hits:

[VHDL-FPGA-Verilog] GPS去载波verilog实现

Description: 该源码用verilog实现gps信号的去载波过程
Platform: | Size: 3582001 | Author: xiaoyannan006@163.com | Hits:

[Software Engineering] verilog50%

Description: 本文主要介绍了50％占空比三分频器的三种设计方法，并给出了图形设计、VHDL设计、编译结果和仿真结果。设计中采用EPM7064AETC44-7 CPLD，在QUARTUSⅡ4.2软件平台上进行。 -This paper introduces a 50% duty cycle three dividers of the three design methods, and gives the graphic design, VHDL design, compile results and the simulation results. Design used EPM7064AETC44-7 CPLD. In QUARTUS II 4.2 software platform.
Platform: | Size: 187392 | Author: li | Hits:

[Software Engineering] FPGA_GPS_C_A

Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.
Platform: | Size: 163840 | Author: xiaozhu | Hits:

[VHDL-FPGA-Verilog] gps_jiance

Description: 合并单元内GPS同步时钟的检测 合并单元内GPS同步时钟的检测-Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection
Platform: | Size: 1024 | Author: 远方 | Hits:

[GPS develop] FPGAdatatransport

Description: 本文设计的FPGA模块需要对GPS、便携打印机和串口数据进行处理，将详细介绍如何设计FPGA和不同外设之间的数据传输。同时，在RTL编码中，编写使综合与布局布线效果更佳的代码。-In this paper, the design of FPGA modules need for GPS, portable printers, and serial data processing, will be details on how to design FPGA and data transfer between peripherals. At the same time, RTL coding, synthesis and preparation to make better placement and routing code.
Platform: | Size: 11264 | Author: zhanyi | Hits:

[GPS develop] c_a

Description: GPS中C/A码产生简单的Verilog逻辑产生-GPS in the C/A code generated simple logic generated Verilog
Platform: | Size: 222208 | Author: 王军 | Hits:

[GPS develop] GPSNaviDataGen_4ch

Description: 基于verilog语言的ＧＰＳ模拟源代码，代码为４颗星，包含噪声信号。-GPS-based Analog Verilog language source code, code for the four stars, including the noise signal.
Platform: | Size: 6144 | Author: Li Gengmin | Hits:

[GPS develop] PcodeGeneration

Description: 在ModelSim或其他支持Verilog语言编译的环境中仿真可得GPS的P码及与卫星数据码调制后的波形，其中一个为源程序，另一个为测试程序-ModelSim or other support in the language Verilog simulation environment to compile available GPS P-code and code of satellite data after the modulation waveform, one for the source, and the other for the test procedure
Platform: | Size: 69632 | Author: tianjieyu | Hits:

[VHDL-FPGA-Verilog] ca

Description: 基于vhdl/verilog的gps接收机伪随机码产生程序。已经过仿真综合。-Based on vhdl/verilog of the gps receiver pseudo-random code generation process. Simulation has been integrated.
Platform: | Size: 1024 | Author: 包鼎华 | Hits:

[VHDL-FPGA-Verilog] ca_gen

Description: 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number, the output generated C/A code. This procedure carried out in the code optimization, take up fewer resources.
Platform: | Size: 1024 | Author: 李殿为 | Hits:

[Modem program] GPS

Description: 用verilog 编写的gps系统调制解调器，很大很实用-Gps system prepared with verilog modem, very very useful
Platform: | Size: 13493248 | Author: 吴雷 | Hits:

[Other] gps

Description: Implement the GPS module time detection function via verilog language.-gps fuction module implemented in xilinx FPGA
Platform: | Size: 5940224 | Author: liu1teng | Hits:

[VHDL-FPGA-Verilog] CODE_GEN

Description: 北斗、GPSC/A码生成器的verilog ，输出速率可调，使用verilog编写- FPGA-based GPS receiver complete code of the spreading code generator design using verilog language
Platform: | Size: 1024 | Author: 刘先生 | Hits:

[VHDL-FPGA-Verilog] BCH_EN

Description: 基于FPGA的GPS/BD信号发生器中BCH编码发生器模块，使用verilog编写- FPGA-based GPS/BD signal generator BCH code generator module, using verilog write
Platform: | Size: 4570112 | Author: 刘先生 | Hits:

[VHDL-FPGA-Verilog] NAVI

Description: 基于fpga的GPS导航数据发生器，使用verilog编写- Fpga-based GPS navigation data generator, using verilog write
Platform: | Size: 1733632 | Author: 刘先生 | Hits:

[assembly language] code_gen

Description: 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。--This program generates Verilog GPS satellite navigation signals for C/A code, the input signal with a clock, clock enable, reset, given the satellite number, the output generated C/A code. This program on code optimization, taking up less resources
Platform: | Size: 2048 | Author: pyy | Hits:

[Other] yuandaima

Description: 以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境-GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II
Platform: | Size: 2130944 | Author: 王秋帆 | Hits:

[VHDL-FPGA-Verilog] CAMA

Description: 基于Verilog语言的GPS卫星PRN1的导航伪码的产生，简单易懂，代码简单。-Generates Verilog language PRN1 GPS satellite navigation based on pseudo-code, easy to understand, simple code.
Platform: | Size: 8262656 | Author: 王超 | Hits:

[android] quiz 1

Description: Radix 2 fft in matlab and verilog.
Platform: | Size: 115712 | Author: Bakchodi | Hits:
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