Search - Verilog HDL ALU

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[Other resource] verilog DL : 0: 8bit alu use verilog hdl
Update : 2008-10-13 Size : 8.55kb Publisher : 周微微
[Other resource] alu-div DL : 0: 用verilog HDL代码编写的快速除法器，比较有用
Update : 2008-10-13 Size : 14.78kb Publisher : 徐芬
[VHDL-FPGA-Verilog] 8051core-Verilog DL : 0: 利用verlilog hdl语言编程，完成了8051内核，非常值得学习硬件描述语言的人看看！-Verlilog hdl programming language to use to complete the 8051 core, very much worth learning hardware description language of the people to see!
Update : 2025-02-17 Size : 52kb Publisher : 小方
[ARM-PowerPC-ColdFire-MIPS] verilog DL : 1: 8bit alu use verilog hdl
Update : 2025-02-17 Size : 8kb Publisher : 周微微
[VHDL-FPGA-Verilog] alu-div DL : 0: 用verilog HDL代码编写的快速除法器，比较有用
Update : 2025-02-17 Size : 15kb Publisher : 徐芬
[VHDL-FPGA-Verilog] alu DL : 0: 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware description language programming ALU181 function arithmetic logic operations, editing Experimental schematic diagram, in the Arithmetic Logic Unit schematic diagram on its expansion into the spaces for arithmetic logic operation unit, its compiler, and the design of their simulation waveforms, and finally download the verification
Update : 2025-02-17 Size : 652kb Publisher : 623902748
[VHDL-FPGA-Verilog] alu DL : 0: 加法器FPGA 实现，精简，快速，高效，有仿真文件-adder base on FPGA ，verilog HDL
Update : 2025-02-17 Size : 1kb Publisher : lijiaming
[VHDL-FPGA-Verilog] ALUALUcontrol DL : 0: 实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
Update : 2025-02-17 Size : 1.01mb Publisher : 于伟
[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24 DL : 0: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Update : 2025-02-17 Size : 4.72mb Publisher : 石
[VHDL-FPGA-Verilog] alu32bit DL : 0: verilog hdl alu module it is 32bit alu and 1bit alu
Update : 2025-02-17 Size : 360kb Publisher : park
[VHDL-FPGA-Verilog] ALUPVERILOG DL : 0: 用verilog HDL语言实现ALU 运行于quartus-ALU using verilog HDL language to run on quartus
Update : 2025-02-17 Size : 1.12mb Publisher : chenyu
[VHDL-FPGA-Verilog] alu DL : 0: It is 32 bit ALU code in Verilog HDL programming Language
Update : 2025-02-17 Size : 1kb Publisher : srikanth
[Other] ALU DL : 0: MIPS ALU written using Verilog HDL. Computer structure project
Update : 2025-02-17 Size : 3kb Publisher : viet
[Software Engineering] lab-1-ALU-design-with-Verilog-HDL DL : 0: cpu设计的运算器部分verilog代码，实验资料，包括原理和代码，在modelsim仿真通过-CPU design arithmetic unit part of the verilog code, experimental data, including the principle and code, through the modelsim simulation
Update : 2025-02-17 Size : 19kb Publisher : 张明明
[Other Embeded program] alu DL : 0: My own arithmetic and logic unit in Verilog HDL.
Update : 2025-02-17 Size : 1kb Publisher : Jain
[Other] alu DL : 0: 用Verilog HDL编写的简单算数逻辑单元-Algorithm Logic Unit programmed by Verilog HDl
Update : 2025-02-17 Size : 43kb Publisher : 张娜
[VHDL-FPGA-Verilog] FloatALU DL : 0: 用Verilog HDL实现的IEEE754浮点数加减乘除法器-float number alu
Update : 2025-02-17 Size : 6.09mb Publisher : 糊糊
[VHDL-FPGA-Verilog] ALU_VERILOG_COCOTB DL : 0: ALU written in Verilog HDL and tester written in python using the cocotb library
Update : 2025-02-17 Size : 3kb Publisher : Nobunaga Chipotle