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Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
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Size: 369497 |
Author: 陈俊 |
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Description: 这是一个Verilog HDL编写的RISC cpu的程序,该程序共10个子程序,实现了简单的RISC cpu,可供初学者参考,学习硬件描述语言,及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which
came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
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Size: 44032 |
Author: 施向东 |
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Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
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Size: 369664 |
Author: 陈俊 |
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Description: 简单的一个8位RISC,Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57
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Size: 80896 |
Author: 陈正一 |
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Description: hrisc cpu,为何只有vhdl选择呢?大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
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Size: 128000 |
Author: 12 |
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Description: 一个支持精简指令的16位的risc cpu,可综合-a directive to support the streamlining of the 16 RISC CPU can be integrated
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Size: 163840 |
Author: 董 |
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Description: Verilog HDL编写的CPU模型,很经典,比较通用-Verilog HDL prepared by the CPU model, classic, more generic
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Size: 1024 |
Author: wyl |
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Description: Verilog HDL编写的总线功能模型,十分有用,需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
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Size: 2048 |
Author: wyl |
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Description: 经典计算机体系结构RISC8的源代码(Verilog),包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register
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Size: 82944 |
Author: snake |
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Description: verilog hdl编写,六段流水线CPU.程序完整,功能强惊。分为多模块编写-verilog hdl prepared replace pipelined CPU. The integrity of the process, strong function scared. Divided into multiple modules prepared
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Size: 656384 |
Author: lumingzhi |
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Description: 在微型计算机系统中, CPU与外部的基本通信方式有两种,一种是并行通信即数据的各位同
时传送,其优点是传输速度较快,但数据有多少位就需要多少条传送线 而串行通信中数据一位一位顺序传
送,能节省传送线. 用Verilog HDL语言实现了串并、并串通信接口之间的转换-In the micro-computer system, CPU and the outside of the basic means of communication there are two types of parallel data communication that is transmitted at the same time you have the advantage of faster transfer speeds, but data on the number of those who need the number of transmission line and string A line of data communications, a sequence of transmission, transmission lines can be saved. using Verilog HDL language and realize the string, and string conversions between the communication interface
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Size: 372736 |
Author: 陈东 |
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Description: 设计CPU方法及流程!VERILOG hdl-CPU design methods and processes! VERILOG hdl
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Size: 208896 |
Author: 正中 |
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Description: 实现16位的cpu设计 内容使用verilog hdl实现,具体的实现步骤方法,都已经写到文档里面去了!-To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
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Size: 440320 |
Author: gimel_sh |
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Description: Verilog HDL编写的4条指令CPU-Verilog HDL prepared four instructions CPU
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Size: 93184 |
Author: liming |
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Description: design cpu 16 bits by verilog HDL.
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Size: 1024 |
Author: tommy |
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Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
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Size: 2048 |
Author: dylan |
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Description: 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器,使其能够支持基本的指令。
2. 用Verilog HDL实现单时钟CPU控制器,在ISE上进行波形仿真,并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-clock with Verilog HDL CPU controller, the ISE on the waveform simulation and FPGA implementation.
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Size: 1024 |
Author: dino |
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Description: MIPS Implementation in Verilog.
Full source code!
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Size: 39936 |
Author: loox_dg
|
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Description: cpu仿真,提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words
in this short file
how can I do?
just tell you the simulated file and vivado system is 2015)
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Size: 200704 |
Author: momotou
|
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Description: CPU设计,已通过模拟,有需要的自行下载吧(CPU design has been simulated)
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Size: 38912 |
Author: sak1tam |
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