Search - Verilog JAVA

[Linux-Unix] sc2v

Description: SystemC to Verilog 转换源程序。-SystemC conversion to Verilog source.
Platform: | Size: 70656 | Author: 吴文河 | Hits:

Description: 设计四拔河游戏机 1、设计一个能进行拔河游戏的电路。 2、电路使用15个(或9个)发光二极管，开机后只有中间一个发亮，此即拔河的中心点。 3、游戏双方各持一个按钮，迅速地、不断地按动，产生脉冲，谁按得快，亮点就向谁的方向移动，每按一次，亮点移动一次。 4、亮点移到任一方终端二极管时，这一方就获胜，此时双方按钮均无作用，输出保持，只有复位后才使亮点恢复到中心。 5、用数码管显示获胜者的盘数。教学提示: 1、按钮信号即输入的脉冲信号，每按一次按钮都应能进行有效的计数。 2、用可逆计数器的加、减计数输入端分别接受两路脉冲信号，可逆计数器原始输出状态为0000，经译码器输出，使中间一只二极管发亮。 3、当计数器进行加法计数时，亮点向右移；进行减法计数时，亮点向左移。 4、由一个控制电路指示谁胜谁负，当亮点移到任一方终端时，由控制电路产生一个信号，使计数器停止计数。 5、将双方终端二极管“点亮”信号分别接两个计数器的“使能”端，当一方取胜时，相应的计数器进行一次计数，这样得到双方取胜次数的显示。 6、设置一个“复位”按钮，使亮点回到中心，取胜计数器也要设置一个“复位”按钮，使之能清零。 -design a tug-of-war game, can design a game of tug of war circuit. 2, circuit use 15 (or 9), light-emitting diodes, come only among a shiny, namely, the center of tug-of-war. 3, the game with a two button rapidly and continuously pressed, have a pulse, who by fast, Who bright spots on the move, every time, a bright spot in Mobile. 4, the party moved to highlight terminal diode, on the winning side, this time the two sides had no effect buttons, to maintain output, so after only bright spot reduction restored to the center. 5, digital Display won the bookkeeping. Teaching Tip : one, that the button signal input pulse signal every time the button should be able to effectively counter. 2, with reversible counter, plus or minus count input to receive two pulse signal, reversible counter to the
Platform: | Size: 292864 | Author: 万金油 | Hits:

[Crack Hack] lfsr

Description: 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] electric-8.08

Description: The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such as VHDL and Verilog -The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:* Custom IC layout* Schematic Capture (digital and analog)* Textual Languages such as VHDL and Verilog
Platform: | Size: 15382528 | Author: 杨晓斐 | Hits:

[Software Engineering] EAUserGuide

Description: 視覺化的塑模工具,Enterprise Architect這套工具，有支援圖形轉換成10種以上的程式語言(ActionScript、Ada、C and C++、C#、Java、Delphi、Verilog、PHP、VHDL、Python、System、C、VB.Net、Visual Basic)與DDL(SQL script)-Visual modeling tool, Enterprise Architect set of tools, support for graphics into more than 10 species of the programming language (ActionScript, Ada, C and C++, C#, Java, Delphi, Verilog, PHP, VHDL, Python, System, C , VB.Net, Visual Basic) and DDL (SQL script)
Platform: | Size: 20547584 | Author: Yu-Kuang CHUNG | Hits:

[Program doc] SPI-in-Verilog-implementation

Description: SPI的Verilog实现(非常的全面和详细，还带有SPI算法的注解).-SPI in Verilog implementation (a very full and detailed, but also with the SPI algorithm annotation).
Platform: | Size: 8192 | Author: 尚林 | Hits:

[VHDL-FPGA-Verilog] subtracter_4

Description: 好还是verilog，现在你记忆可以，是关于FPGA的设计-Good or verilog, now you can remember, is the design on the FPGA
Platform: | Size: 100352 | Author: 杨希 | Hits:

[Linux-Unix] netfpga_full_3_0_1.tar

Description: NetFPGA开发基础包，里面有相关的实例工程，也有相关的源码，verilog HDL，C，JAVA等-NetFPGA development base package, there are examples of related works, there are also relevant source, verilog HDL, C, JAVA, etc.
Platform: | Size: 5661696 | Author: 聂晓辉 | Hits:

[JSP] eclispe

Description: 随着对信息化及硬件设备的发展，人们对verilog HDL的使用逐步的用的更加频繁。然而目前的verilog HDL 编辑工具发展相对落后。限制了硬件编程的效率，所以本次通过这些插件的设计可以强大Eclipse的实用功能，使硬件编辑工具有更高的效率。在充分研究Eclipse IDE环境基础上，实现Verilog HDL插件移植，并能实现优惠插件设计实现，参照该环境下Java程序编写中出现的界面优化技术，关键字插件设计，模块查询插件设计等功能。提高硬件语言在该环境下的编程效率。并通过最终对Verilog HDL编写中关键字设计、界面优化技术实现的验证。旨在使Verilog HDL的使用更加方便，并为进一步的应用开发打下基础。-With information technology and hardware development, people use verilog HDL gradually with the more frequent. However, there is a verilog HDL editing tools is relatively undeveloped. Limiting the hardware programming efficiency, so these useful features of this powerful Eclipse plug-ins designed to make hardware more efficient editing tools. Eclipse IDE environment in the full study, based on Verilog HDL realize plug-transplant, and to achieve preferential plug-in design implementation, optimization techniques, keyword plug-in design, modular plug-in design features such as reference inquiries under the Java programming environment in the screen that appears. Improve the efficiency of hardware-language programming in the environment. And ultimately Verilog HDL prepared by keyword design, interface optimization technology validation. Designed to make it easier to use Verilog HDL, and lay the foundation for further application development.
Platform: | Size: 290816 | Author: 陈方 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Linux-Unix] sc2v

[VHDL-FPGA-Verilog] bahe

[Crack Hack] lfsr

[VHDL-FPGA-Verilog] electric-8.08

[Software Engineering] EAUserGuide

[Program doc] SPI-in-Verilog-implementation

[VHDL-FPGA-Verilog] subtracter_4

[Linux-Unix] netfpga_full_3_0_1.tar

[JSP] eclispe

[Internet-Network] Java--8268192Verilog--9726PLANER-41

[ERP-EIP-OA-Portal] LFSRTestbench

[Delphi VCL] ecrvvtre 帮助文档

CodeBus www.codebus.net