Search - Verilog USB host

Search - Verilog USB host - List

[Other resource] usbhostslave DL : 0: USB主机和设备的verilog代码，实现了USB1.1协议规范的要求-USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements
Update : 2008-10-13 Size : 489.3kb Publisher : 张雷
[Other Embeded program] usbhostslave DL : 0: Update : 2025-03-15 Size : 489kb Publisher : 张雷
[USB develop] USB2_chip DL : 0: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Update : 2025-03-15 Size : 35kb Publisher : 戴鹏
[Embeded-SCM Develop] DE2_NIOS_HOST_MOUSE_VGA DL : 0: 利用该源代码可以实现在DE2的板子上进行USB画笔的实验-use of the source code can be achieved in the board Dictyophora USB brush on the experiment
Update : 2025-03-15 Size : 1kb Publisher : 杨阿胡
[VHDL-FPGA-Verilog] WORKS DL : 0: Project of Adquisition Data, show in VGA and send to usb host
Update : 2025-03-15 Size : 9.46mb Publisher : lagartojj
[Other] usb DL : 0: USB slave: It is contain a USB slave design written in verilog language. It is a interface between USB host and Functions such as memory, Keyboard, mouse and so on.-SB slave: It is contain a USB slave design written in verilog language. It is a interface between USB host and Functions such as memory, Keyboard, mouse and so on.
Update : 2025-03-15 Size : 226kb Publisher : william
[VHDL-FPGA-Verilog] usb_host1 DL : 0: verilog 的主机访问程序，与设备端程序配套，已验证-verilog for usb host
Update : 2025-03-15 Size : 27kb Publisher : hehehaha2014
[VHDL-FPGA-Verilog] usb_rd_buffer DL : 0: FPGA（SPARTAN6）通过USB协议与开发板上的USB芯片进行数据读写测试，在上位机上可以看到USB发来的数据，也可以通过修改VERILOG代码完成数据的接收(FPGA (SPARTAN6) can read and write data through the USB chip on the development board through the USB protocol. The data sent by USB can be seen on the host computer, and the data can be received by modifying the VERILOG code)
Update : 2025-03-15 Size : 4.21mb Publisher : marktuwen