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[Other resource] DE2_TV

Description: 一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
Platform: | Size: 26953 | Author: 李全 | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
Platform: | Size: 26624 | Author: 李全 | Hits:

[Graph Recognize] saa7113shipincaiji

Description: 视频图像采集verilog HDl源程序，视频解码芯片部分的，可以供参考-Video image acquisition verilog HDl source, part of the video decoder chip, you can for reference
Platform: | Size: 8192 | Author: 穆垚 | Hits:

[Streaming Mpeg4] H.264

Description: 本书在介绍数字视频和视频编码的基本原理基础上，论述了H264的特点、编码器原理、解码器原理以及编解码器的实现方案。-This book, introducing digital video and video encoding based on the basic principles, discusses the characteristics of H264, encoder principle, the principle of the decoder and codec realization of the program.
Platform: | Size: 11018240 | Author: 许菀纯 | Hits:

[VHDL-FPGA-Verilog] I2C_Controller

Description: 对视频编解码芯片ADV7181进行合理的配置，使其输出符合ITUR656标准的视频流-Of the ADV7181 video decoder chip for a reasonable configuration, so that the output in line with the standard video streaming ITUR656
Platform: | Size: 1024 | Author: 黄涛 | Hits:

[Compress-Decompress algrithms] MQdecoder

Description: Verilog HDL 实现的JPEG200的MQ解码-JPEG2000 MQ DECODER BASED ON FPGA， Verilog HDL
Platform: | Size: 1518592 | Author: 林木 | Hits:

[VHDL-FPGA-Verilog] xapp288

Description: This the reference design file for XAPP288 " SDI Video Decoder" it includes both VHDL and Verilog versions -This is the reference design file for XAPP288 " SDI Video Decoder" it includes both VHDL and Verilog versions
Platform: | Size: 68608 | Author: zhangxinxin | Hits:

[VHDL-FPGA-Verilog] 61EDA

Description: 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌 入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案， 针对视频解码芯片 ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII 系列FPGA(EP2C35)上实现。结果显示本设计具有速度高、成本低、易于集成等优点-Analysis of a variety of video capture programs reviewed. On how to use CCD camera capture high-resolution, high-quality images, as well as FPGA-based embedded video image acquisition system realization method was studied. Used to camera mode+ decoder chip collection program for video decoder chip ADV7181B, realized the I2C bus configuration, ITU656 decoder, VGA display module design. The video capture controller has been designed in the Altera' s CycloneII series FPGA (EP2C35) to achieve. The results showed that this design has a high speed, low cost, easy to integrate the advantages of
Platform: | Size: 179200 | Author: 李明 | Hits:

[mpeg mp3] H.264

Description: 关于h.264视频解码器完全源码（verilog）-With regard to h.264 video decoder full source code (verilog)
Platform: | Size: 836608 | Author: 李风志 | Hits:

[VHDL-FPGA-Verilog] LIP6431CORE_NTSC_Video_Decoder

Description: NTSC Video Decoder Verilog Source code
Platform: | Size: 1537024 | Author: jc | Hits:

[VHDL-FPGA-Verilog] Div3

Description: 一个除3器的Verilog源码，用于视频解码器的熵解码部分。纯组合逻辑，大小和加法器差不多。-In addition to device a Verilog source code 3, the video decoder for entropy decoding part. Pure combinational logic, about the size and adder.
Platform: | Size: 106496 | Author: 闫煜 | Hits:

[VHDL-FPGA-Verilog] LIP6421CORE_video_decoder

Description: Video decoder verilog source code
Platform: | Size: 12680192 | Author: jc | Hits:

[VHDL-FPGA-Verilog] tst_saa7113h

Description: 飞利浦的视频解码芯片SAA7113H的Verilog控制源代码，该源代码加入了SRAM和DSP，很值得参考-The Verilog control code of Philips video decoder chip SAA7113H , the source code combine the interface of SRAM and DSP, it is worth considering
Platform: | Size: 8192 | Author: GC | Hits:

[VHDL-FPGA-Verilog] i2c_1.tar

Description: i2c driver for video decoder ad9980 in virtex
Platform: | Size: 1604608 | Author: Minesh | Hits:

[VHDL-FPGA-Verilog] bluespec-h264_latest.tar

Description: H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
Platform: | Size: 16858112 | Author: YUKAI ZHANG | Hits:

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