Search - Verilog ddc

Search - Verilog ddc - List

[Com Port] ddc_scl_detect DL : 1: 显示器ddc数据通道的时钟和数据信号检测的Verilog代码。
Update : 2010-11-01 Size : 874byte Publisher : yangguotao
[GPS develop] ddc_simu DL : 0: ddc simulation 进行DDC实现过程的仿真-ddc simulation DDC realization process for the simulation
Update : 2025-03-14 Size : 1kb Publisher :
[Other] GC4016 DL : 0: GC4016 DDC Chip GC4016
Update : 2025-03-14 Size : 207kb Publisher : 张晋
[Program doc] ddc DL : 0: 介绍了一种基于软件无线电思想的频分多址中频数字化接收机系统设计方案。它采用Altera公司的FPGA构成核心单元,通过不同的软件配置实现对三路频分多址信号的解调。 -Introduce a software-based radio thinking FDMA digital IF receiver system design. It uses Altera s FPGA constitute the core unit, through different software configuration for the three-way realize FDMA signal demodulation.
Update : 2025-03-14 Size : 797kb Publisher : 可难
[Software Engineering] AD6634DDC DL : 0: DDC design based on AD6634,useful-DDC design based on AD6634, useful
Update : 2025-03-14 Size : 39kb Publisher : 岳翔
[Communication-Mobile] DDC DL : 1: 个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR-DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
Update : 2025-03-14 Size : 2kb Publisher : yeong
[matlab] DDC DL : 0: 用6阶CIC实现，加噪声仿真。序内加详尽注释。-6 bands CIC realized, plus noise simulation. Sequence with a detailed note.
Update : 2025-03-14 Size : 2kb Publisher : yeong
[Compress-Decompress algrithms] DDC DL : 0: matlab与synplify DSP AE相结合的DDC实例，希望对大家有所帮助-matlab and synplify DSP AE combining DDC example, in the hope that U.S. help
Update : 2025-03-14 Size : 183kb Publisher : luocaijin
[matlab] cic_M DL : 0: CIC filter setup, this is special used for the DDC
Update : 2025-03-14 Size : 7kb Publisher : 朱天翔
[VHDL-FPGA-Verilog] DDC DL : 0: verilog语言实现的数字下变频设计。在ALTERA的QUARTUS ii下实现。实用，好用。-Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
Update : 2025-03-14 Size : 43kb Publisher : 咚咚
[assembly language] wddc_module DL : 0: 数字下变频的Verilog程序，测试可以直接使用，将A/D信号下变频为基带I，Q两路信号-Digital down conversion of the Verilog program, testing can be used directly to A/D signal down-conversion to baseband I, Q signals two
Update : 2025-03-14 Size : 3kb Publisher : gaigai
[Multimedia program] DDC_FilterChain_HDL DL : 0: simulink demo of ddc
Update : 2025-03-14 Size : 169kb Publisher : bnpvas
[Software Engineering] ddc DL : 0: 随着数模转换器硬件的快速发展和DSP处理能力及处理速度的逐步提高，软件无线电技术在商用和军用无线电通信领域也越来越显示出其强大的吸引力。本文研究的高速中频采样和数字下变频技术是目前蓬勃发展的软件无线电领域的两项关键技术。-As advances in technology provide increasingly faster and less expensive digital hardware, more of the traditionally analog functions of a radio receiver will be replaced with software or digital hardware. The software radio has show its fascinating functions in both commercial and military wireless communication. The high speed and high resolution analog-to-digital converter and digital down-converter which are researched in this thesis are two of the key technologies in the field of software radio that is vigorously developing recently.
Update : 2025-03-14 Size : 2.53mb Publisher : zc
[Other] DDC DL : 0: Digital Down Covertor Documents
Update : 2025-03-14 Size : 1.42mb Publisher : Kiran
[VHDL-FPGA-Verilog] RealizationofdigitaldownconversionbyFPGA DL : 0: 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the preparation of some call a combination of IP core method of the FPGA digital down conversion method, and completed its main modules of simulation and debugging, and initial system-level verification.
Update : 2025-03-14 Size : 159kb Publisher : 于银
[Embeded-SCM Develop] verilog_FPGA_DDC DL : 0: 这是一个用verilog HDL实现的实现数字下变频的源代码。-This is a verilog HDL used to achieve the realization of digital down conversion of the source code.
Update : 2025-03-14 Size : 2.66mb Publisher : 王坤
[matlab] ddc DL : 0: DDC仿真模型，利用systemgenerator实现数字下变频-DDC simulation model, the use of digital down-conversion systemgenerator
Update : 2025-03-14 Size : 16kb Publisher : 曾重阳
[3G develop] GSM_DDC DL : 0: GSM中数字下变频器的matlab辅助设计，并可以采用matlab生成verilog代码。-GSM digital down converter in the matlab-aided design, and can be used matlab generate verilog code.
Update : 2025-03-14 Size : 307kb Publisher : 张勇奇
[OA] ddc DL : 0: 仿真了DDC的工作流程，不了解数字下变频的朋友可以下载-DDC emulation of the workflow, do not understand the digital down-conversion can be downloaded to see if a friend
Update : 2025-03-14 Size : 1kb Publisher : 郑程
[Software Engineering] ddc DL : 0: 电子科大2009-应用于无线电监测的高速信号处理平台设计，软件无线电的DDC的FPGA实现！-UESTC 2009- applies to wireless monitoring of high-speed signal processing platform design, software radio DDC' s FPGA implementation!
Update : 2025-03-14 Size : 4.6mb Publisher : peter

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