Search - Verilog for Digital Design

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[Develop Tools] Verilog Coding Style for Efficient Digital Design. DL : 0: Verilog Coding Style for Efficient Digital Design
Update : 2008-10-13 Size : 79.06kb Publisher : 虞亮
[Books] Verilog Coding Style for Efficient Digital Design. DL : 0: Verilog Coding Style for Efficient Digital Design
Update : 2025-02-17 Size : 79kb Publisher : 虞亮
[VHDL-FPGA-Verilog] VHDL语言100例详解 DL : 0: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Update : 2025-02-17 Size : 6.33mb Publisher : 穆群生
[Other] VerilogHDL-2ndEd DL : 0: 是一本好书,verilog HDL,a guide to digital design and synthesis-is a good book, verilog HDL, a guide to digital design and synthesis
Update : 2025-02-17 Size : 1.64mb Publisher : zhanghua
[VHDL-FPGA-Verilog] verilog DL : 0: 这是一个用verilog语言设计的数字频率及的源代码，上传一下，供大家研究 -This is a design using Verilog language and the digital frequency of the source code, upload click for U.S. research
Update : 2025-02-17 Size : 417kb Publisher : bbbbbbbb
[VHDL-FPGA-Verilog] alu181 DL : 0: alu运算器vhdl代码，介绍了16中运算方法，可用于cpu的设计中-alu calculator VHDL code, introduction of 16 in computing methods, can be used for the design of cpu
Update : 2025-02-17 Size : 1kb Publisher : 赵心
[VHDL-FPGA-Verilog] LC3-VHDL-another DL : 0: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Update : 2025-02-17 Size : 790kb Publisher : guo
[VHDL-FPGA-Verilog] Models_and_Testbenches_11_10_2004 DL : 0: VerilogHDL高级数字设计书中源代码适合学习verilog编程者学习-VerilogHDL advanced digital design book learning Verilog source code for programmers to learn
Update : 2025-02-17 Size : 465kb Publisher : yckai
[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga DL : 0: 基于FPGA的多功能数字钟的设计与实现内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Update : 2025-02-17 Size : 3.14mb Publisher :
[VHDL-FPGA-Verilog] adder_32 DL : 1: 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
Update : 2025-02-17 Size : 1kb Publisher : zhaohongliang
[Other] VerilogHDL DL : 0: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Update : 2025-02-17 Size : 78kb Publisher : sundan
[Industry research] UART_DESIGN DL : 0: The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal Asynchronous Receiver & Transmitter).
Update : 2025-02-17 Size : 138kb Publisher : ltrko9kd
[VHDL-FPGA-Verilog] ebook_verilog_fine_state_machine DL : 0: Designing a synchronous finite state machine (FSM) is a common task for a digital logic engineer. This paper discusses a variety of issues regarding FSM design using Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and different methodologies are compared using real-world examples.
Update : 2025-02-17 Size : 119kb Publisher : rex
[VHDL-FPGA-Verilog] book DL : 0: Verilog HDL与VHDL都是数字系统设计的硬件描述语言，VerilogHDL适合算法级，rtl，逻辑级，门级，而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware description language, VerilogHDL suitable algorithm level, rtl, logic level, gate-level, and large VHDL for system-level design. In response to these characteristics of these two books in simple terms to introduce the two languages.
Update : 2025-02-17 Size : 14.84mb Publisher : 龙英
[VHDL-FPGA-Verilog] Digital_System_Design_with_SystemVerilog(draft).ra DL : 0: This book is intended as a student textbook for both undergraduate and postgraduate students.-This book is intended as a student textbook for both undergraduate and postgraduate students. The majority of Verilog and SystemVerilog books are aimed at practicing engineers. Therefore, some features of SystemVerilog are not described at all in this book. Equally, aspects of digital design are covered that would not be included in a typical SystemVerilog book.
Update : 2025-02-17 Size : 1.79mb Publisher : jiaquan
[Other] digital-design-and-synthesis DL : 0: Verilog HDL 数字设计与综合，夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证，不仅讲解语法，更从基本概念讲起，逐渐过渡到编程语言接口以及逻辑综合等高级主题。-The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis.
Update : 2025-02-17 Size : 11.61mb Publisher : huluobo
[Other] Verilog-HDL-Guide-to-Digital-Design DL : 0: Verilog HDL--Guide to Digital Design and Synthesis (2ndEd) ASIC设计与验证领军人物 Samir Palnitkar的Verilog HDL优秀国外电子教材，国内夏宇闻老师那本Verilog教材的参考书籍，对于初学者有很大帮助！-Verilog HDL- Guide to Digital Design and Synthesis (2ndEd) ASIC design and verification leading figures Samir Palnitkar the Verilog HDL outstanding foreign e-learning materials, domestic Xia Wen teacher of the Verilog materials reference books of great help for beginners!
Update : 2025-02-17 Size : 3.2mb Publisher : 杨光
[VHDL-FPGA-Verilog] Verilog-testbench-and-memory-I2C DL : 0: verilog编写的测试平台，内含具体project和储存模块的编写-Verilog testbench for digital design Memory I2C module Assignment
Update : 2025-02-17 Size : 473kb Publisher : ligang
[Other] AshendenDigital-Design---An-Embedded-Systems-Appr DL : 0: Verilog book for digital design
Update : 2025-02-17 Size : 1.77mb Publisher : Raj
[VHDL-FPGA-Verilog] Verilog数字系统设计教程(第2版) DL : 0: 适合学习fpga的童鞋们，verilog语言数字系统设计，一本很不错的学习资料。(Suitable for learning fpga children's shoes, verilog language digital system design, a very good learning materials.)
Update : 2025-02-17 Size : 42.06mb Publisher : 斌河时代

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