Search - Verilog modem

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[DSP program] Blackfin_SpeechAudio DL : 0: 在ADI的Blackfin系列DSP上编写的语音＆音频程序-the ADI Blackfin DSP series on the preparation of voice & audio program! !
Update : 2025-02-17 Size : 466kb Publisher : 李里
[VHDL-FPGA-Verilog] shuzhijietiaoqu DL : 0: 基于FPGA的全数字调制解调器设计实例，包含有Matlab程序和Quartus程序-FPGA-based all-digital modem design example, contains the procedures and Quartus program Matlab
Update : 2025-02-17 Size : 641kb Publisher :
[Other Embeded program] 2400verilog DL : 0: 我刚完成的基于Quartus Two 开发环境全部用Verilog硬件描述语言编译无误的MSK调制解调器-I have just completed development environment based on the Quartus Two full use Verilog hardware description language compiler unmistakable MSK modem
Update : 2025-02-17 Size : 27kb Publisher : lgl
[VHDL-FPGA-Verilog] 2fsk_final DL : 0: 全数字fsk调制解调的实现 verilog源码-All-digital realization of fsk modem verilog source code
Update : 2025-02-17 Size : 659kb Publisher : liulei
[VHDL-FPGA-Verilog] RD1011_rev01.2 DL : 0: 采用VHDL实现的UART硬件模块，该模块包括了modem的硬件实现，已经仿真测试代码，顶层模块可以采用VHDL或verilog实现，便于嵌入到自己的设计之中。文档中附有详细的使用说明和注释。-Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog to achieve easy embedded into the design of their own. Document with detailed instructions and notes.
Update : 2025-02-17 Size : 212kb Publisher : pd
[VHDL-FPGA-Verilog] ofdm DL : 0: ofdm调制解调的fpga实现。使用Verilog实现IEEE 802.16a系统的调制解调模块。-ofdm modulation and demodulation of fpga implementation. Verilog implementation using IEEE 802.16a system, modem module.
Update : 2025-02-17 Size : 2kb Publisher : 张维
[Modem program] GPS DL : 0: 用verilog 编写的gps系统调制解调器，很大很实用-Gps system prepared with verilog modem, very very useful
Update : 2025-02-17 Size : 12.87mb Publisher : 吴雷
[OS Develop] SC16C752B DL : 0: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s (3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics.
Update : 2025-02-17 Size : 157kb Publisher : 刘伟
[VHDL-FPGA-Verilog] FPGA DL : 1: 基于FPGA的通信系统调制解调，包括理论知识介绍和VHDL程序。包含2ASK ,2FSK，2PSK -FPGA-based modem communication systems, including the introduction of theoretical knowledge and the VHDL program. Contains 2ASK, 2FSK, 2PSK
Update : 2025-02-17 Size : 593kb Publisher : songlina
[Communication-Mobile] code DL : 1: <基于Verilog HDL的通信系统设计>源码，包含ASK,FSK,PSK,QPSK,PPM等的调制解调-< Verilog HDL-based communication system design> source, including ASK, FSK, PSK, QPSK, PPM and other modem
Update : 2025-02-17 Size : 6kb Publisher : cjl
[Modem program] QPSKmodulationanddemodulation DL : 0: 这是一个QPSK比较完整的FPGA工程，是用Verilog语言写的，主要包括调制解调模块。-This is a QPSK FPGA project is written in Verilog language, including the modem module.
Update : 2025-02-17 Size : 445kb Publisher :
[VHDL-FPGA-Verilog] QPSK DL : 0: QPSK调制是数字调制解调中最为常见的调制方式之一，此Verilog 文件可以在FPGA上实现QPSK的调制方式-QPSK modulation is one of the most common digital modem modulation scheme, this Verilog file QPSK modulation scheme can be implemented on FPGA
Update : 2025-02-17 Size : 1kb Publisher : 陆从乐
[VHDL-FPGA-Verilog] qpsk-modulation--achieved-by-Verilog DL : 0: qpsk的调制解调的Verilog实现,用Verilog语言来编写实现qpsk调制的实现，已经经过仿真通过。-qpsk modem s Verilog implementation using Verilog language to write achieve qpsk modulation implementation has passed through simulation.
Update : 2025-02-17 Size : 4kb Publisher : daruili
[Program doc] 256qam DL : 1: Quartus II开发套件，256qam的Verilog仿真，有编码和解码过程-Quartus II，256qam，Verilog，Modem，Demodem
Update : 2025-02-17 Size : 3kb Publisher : 宾芬