Search - Verilog pwm

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[Embeded-SCM Develop] pwm发生器 DL : 0: pwm发生器（原理图,pcb，程序流程图，源码80kc196）--PWM generator, including diagram, pcb, data flow diagram , and source code 80kc196).
Update : 2025-02-17 Size : 64kb Publisher : 张晓亮
[VHDL-FPGA-Verilog] verilog hdl教程135例 DL : 0: 浅显易懂的vrilogHDL的程序，可以帮助你迅速上手-Easy and simple VerilogHDL programs to help you to get to the language quickly.
Update : 2025-02-17 Size : 155kb Publisher : 陈浩东
[VHDL-FPGA-Verilog] pwmled DL : 0: 一个霹雳灯的Verilog源程序，用PWM原理实现，产生了LED灯的渐弱效果-a thunderbolt lights Verilog source files, using PWM principle realized, LED lights have a gradual effect of the weak
Update : 2025-02-17 Size : 499kb Publisher : 张伟
[MiddleWare] pwm_VerilogHDLV1.1 DL : 0: 本软件在CPLD上实现数字PWM控制，用Verilog HDL语言编写，在MAX　ＰＬＵＳ　ＩＩ调试成功，可用-the software on the CPLD digital PWM control, using Verilog HDL language, MAX PLUS II in debugging success can be
Update : 2025-02-17 Size : 227kb Publisher : wjz
[VHDL-FPGA-Verilog] PWM DL : 1: 自己写的一个pwm模块，verilog的，是用于无刷电机控制的。-Himself wrote a pwm module, verilog is used for brushless motor control.
Update : 2025-02-17 Size : 3kb Publisher : 李凯
[VHDL-FPGA-Verilog] PWM DL : 1: Core_PWM,verilog语言编写，可用于电机驱动-Core_PWM, verilog language, can be used for motor drive
Update : 2025-02-17 Size : 4.78mb Publisher : zhan
[VHDL-FPGA-Verilog] PWM DL : 0: Core_PWM,verilog语言编写，可用于电机驱动-Core_PWM, verilog language, can be used for motor drive
Update : 2025-02-17 Size : 2kb Publisher : zhan
[VHDL-FPGA-Verilog] cpld-pwm DL : 0: 基于cpld的pwm控制设计采用vhdl.verilog语言设计对大家比较有用-CPLD-based control design uses the pwm design vhdl.verilog language more useful for everyone
Update : 2025-02-17 Size : 78kb Publisher : emily
[VHDL-FPGA-Verilog] PWM DL : 0: 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
Update : 2025-02-17 Size : 2kb Publisher : 望习才
[VHDL-FPGA-Verilog] servo_module_worked DL : 0: verilog pwm to control servo motor on quartus
Update : 2025-02-17 Size : 21kb Publisher : frankie
[VHDL-FPGA-Verilog] PWM DL : 0: verilog pwm to control servo motor on quartus, with microprocessor generated from sopc and connected with sram-verilog pwm to control servo motor on quartus
Update : 2025-02-17 Size : 21kb Publisher : frankiecoco
[VHDL-FPGA-Verilog] pwm DL : 0: verilog实现PWM 开发环境 QUARTUS II7.0-verilog to achieve PWM development environment QUARTUS II7.0
Update : 2025-02-17 Size : 53kb Publisher : exun
[SCM] pwm DL : 0: pwm的占空比和死区时间可调的Verilog HDL程序设计和测试-duty cycle of pwm and adjustable dead time of the Verilog HDL design and testing procedures
Update : 2025-02-17 Size : 1kb Publisher : chenhaoran
[VHDL-FPGA-Verilog] PWM-OUT DL : 0: 这里是一个比较好的用Verilog写的通过按键控制PWM输出从而控制小灯亮灭程度的经典例子~！~-Here is a better written in Verilog by using buttons to control the PWM output level of the control of small lights eliminate the classic example of ~! ~
Update : 2025-02-17 Size : 304kb Publisher : ll
[VHDL-FPGA-Verilog] pwm DL : 0: 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
Update : 2025-02-17 Size : 3kb Publisher : 尹长生
[VHDL-FPGA-Verilog] PWM DL : 0: 一个用Verilog实现PWM硬件的开发实例 -PWM hardware using Verilog implementation of a development instance
Update : 2025-02-17 Size : 23kb Publisher : lsh
[VHDL-FPGA-Verilog] PWM DL : 0: verilog描述 PWM IP核内部包括载波占空比和时能寄存器-IP kernel of PWM based on Verilog hdl
Update : 2025-02-17 Size : 4kb Publisher : 胡静
[VHDL-FPGA-Verilog] PWM DL : 0: 利用Verilog语言设计一个PWM控制器，实现：控制器输入时钟1MHz；控制器输出脉冲周期1kHz，脉宽最小调节步长0.1%。(The Verilog language is used to design a PWM controller, which is realized: the controller input clock 1MHz; the controller output pulse cycle 1kHz, and the pulse width minimum adjustment step 0.1%.)
Update : 2025-02-17 Size : 61kb Publisher : jcg17
[SCM] pwm控制直流电机_verilog_l9110 DL : 0: VERILOG语言控制的直流电机在各大数字逻辑软件如VIVADO ise 均可使用功能强大简单易学(motor controlled by VERILOG HDL)
Update : 2025-02-17 Size : 10kb Publisher : 铭润
[VHDL-FPGA-Verilog] pwm DL : 0: 本程序可以实现输出不同占空比（0-100）和不同频率的pwm波形；满足驱动不同硬件的需求；(This program can output PWM waveforms with different duty cycles (0-100) and different frequencies, and meet the needs of different hardware drivers.)
Update : 2025-02-17 Size : 7.12mb Publisher : DA北岛

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