Search - Verilog scrambler

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[Other resource] scrambler DL : 0: 通信系统中的加扰与解扰程序，用verilog语言实现，有波形文件可以直接查看功能
Update : 2008-10-13 Size : 316.47kb Publisher : 桃子
[Other resource] pn_code DL : 0: 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures
Update : 2008-10-13 Size : 35.74kb Publisher : 高广鹤
[VHDL-FPGA-Verilog] pn_code DL : 0: 系数为4的扰码生成器，并每四位扰码产生一个触发串并转换的触发信号，可用于4b/5b编码的触发信号。verilog程序，带test程序-coefficient of the four scrambler generator, and every four scrambler have triggered a string conversion and the trigger signal can be used to trigger 4b/5b coding signal. Verilog procedures, with test procedures
Update : 2025-02-17 Size : 35kb Publisher : 高广鹤
[VHDL-FPGA-Verilog] scrambler DL : 0: 通信系统中的加扰与解扰程序，用verilog语言实现，有波形文件可以直接查看功能-Communication Systems scrambling and descrambling process, with Verilog language, has waveform files can be directly read features
Update : 2025-02-17 Size : 316kb Publisher : 桃子
[VHDL-FPGA-Verilog] bluetooth DL : 0: ip核，蓝牙bluetooth的fpga硬件实现-ip nuclear, Bluetooth bluetooth realize the FPGA hardware
Update : 2025-02-17 Size : 16kb Publisher : 惠普
[VHDL-FPGA-Verilog] SCRAMBLER DL : 0: 32位扰码器的verilog代码，编译通过-The Verilog code of 32_bit scrambler
Update : 2025-02-17 Size : 1kb Publisher : 朱猪
[VHDL-FPGA-Verilog] DATA_scramble DL : 0: 扰码器的verilog实现,参考802.11a相关标准-Scrambler in verilog implementation
Update : 2025-02-17 Size : 1kb Publisher :
[VHDL-FPGA-Verilog] scrambler_17 DL : 0: this parallel scrambler verilog code -this is parallel scrambler verilog code
Update : 2025-02-17 Size : 315kb Publisher : rakhi
[VHDL-FPGA-Verilog] yuanchengxu DL : 0: 基于Verilog HDL的通信系统设计-Design of communication system based on Verilog HDL
Update : 2025-02-17 Size : 48kb Publisher : lnf
[ELanguage] bin_count DL : 0: i m sending hdl code of dm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.-i m sending hdl code of ofdm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.
Update : 2025-02-17 Size : 28kb Publisher : Nilesh panchal
[VHDL-FPGA-Verilog] scrambler DL : 0: Verilog编写的ADC加扰程序（scrambler）里边附有加扰器的说明，实验可以把数据打散，可自行写testbench测试-Verilog prepared by the ADC scrambled program (scrambler) inside with scrambler description, experimental data can be broken up, write their own testbench test
Update : 2025-02-17 Size : 216kb Publisher : 王红伟