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[VHDL-FPGA-Verilog] SystemOfTaxiFeeBasedOnVerilogHDL

Description: 摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ-Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ
Platform: | Size: 211968 | Author: 杨轶帆 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: ：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。-: A Shanghai taxi meter area for example, the use of Verilog HDL language taxi meter is designed so that it will have the time display, billing and simulated taxi start, stop, reset and other functions, and set up the dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the advantages of digital logic circuits. Source by the MAX+ PLUS Ⅱ software debugging, optimization, download EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system.
Platform: | Size: 211968 | Author: mindy | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: Verilog编写的出租车计价器程序，可以设置按路程计价，按等待时间计价。非常方便，界面良好-Verilog program, prepared a taxi meter can be set according to distance pricing, valuation by waiting time. Very convenient, good interface
Platform: | Size: 2170880 | Author: 牟星光 | Hits:

[VHDL-FPGA-Verilog] dianzixianlu

Description: 出租车计费器Verilog程序，比较简单的计费功能。-Taxi meter Verilog program, simple billing functions.
Platform: | Size: 3453952 | Author: 李明 | Hits:

[VHDL-FPGA-Verilog] taxi

Description: 出租车自动计费器，使用verilog hdl语言编写，计费包括起步费、里程费、等待费，并利用八位数码管显示。-Automatic meter taxi, using verilog hdl language, including start charging fees, mileage fees, waiting costs, and use eight digital display.
Platform: | Size: 7947264 | Author: 金若梅 | Hits:

[VHDL-FPGA-Verilog] chuzuche

Description: 本程序使用verilog语言编写的出租车计价系统，实现时距并计！主要用状态机来实现！-This program uses the taxi meter verilog language system, and taking into account the time-distance! State machine is mainly used to achieve!
Platform: | Size: 1487872 | Author: 欢欢 | Hits:

[VHDL-FPGA-Verilog] taxi

Description: 利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。-Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.
Platform: | Size: 279552 | Author: jonette | Hits:

[VHDL-FPGA-Verilog] verilogClassicSamples

Description: verilog常用程序及其仿真结果整理，包括LCD，LED，AD采集，URAT，电子琴，电梯控制，自动售货机控制，出租车计价器，电子时钟，频率计，MPSK调制与解调-verilog common finishing process and its simulation results, including LCD, LED, AD collection, URAT, keyboard, elevator control, vending machine control, taxi meter, electronic clock, frequency counter, MPSK modulation and demodulation, etc.
Platform: | Size: 1278976 | Author: ZhangYan | Hits:

[Windows Develop] Utaxis

Description: 用verilog写的基于cpld的出租车计费器的源源码，需要的参考一下 ，经测试可直接使用。 -Verilog write source based the cpld taxi meter source reference, the test can be used directly.
Platform: | Size: 1286144 | Author: 干预 | Hits:

[VHDL-FPGA-Verilog] texi

Description: 出租车计费器。verilog语言设计，合理利用了de2开发板资源，功能全面-Taxi meter. verilog language design
Platform: | Size: 1360896 | Author: zzh | Hits:

[VHDL-FPGA-Verilog] taxi

Description: verilog实现出租车计费功能，起步价、里程数、等待时间计算-Verilog taxi meter function, starting price, mileage, waiting time
Platform: | Size: 451584 | Author: passerby9091 | Hits:

[Other] car

Description: 运用Verilog语言，用quartus及niosII的的开发环境，实现了出租车计费器的设计-Using Verilog language, using quartus and niosII the development environment, to achieve a taxi meter design
Platform: | Size: 13818880 | Author: 涂丽芳 | Hits:

[Other Embeded program] Taximeter

Description: 出租车计价器（其中包括分频模块，计程模块，计时模块，计费模块，显示模块以及顶层模块），基于Verilog HDL语言，开发板是FPGA(Sparten 6 LXS45),开发环境是Xilinx。-Taxi meter (including frequency module, the meter module, timing module, billing module, display module and top-level module), based on Verilog HDL language, the development board is FPGA (Sparten 6 LXS45), the development environment is Xilinx.
Platform: | Size: 3443712 | Author: 胡玉 | Hits:

[VHDL-FPGA-Verilog] taxifee

Description: 用Verilog语言完成出租车计价器的功能-Verilog language used to complete the taxi meter function
Platform: | Size: 1025024 | Author: | Hits:

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