Search - Vhdl servo

[VHDL-FPGA-Verilog] vcpwmcpldcar

Description: vc++与vhdl代码,cpld接受pc串口指令,输出pwm信号控制伺服电机.双通道,各128级.使用了扩展ascii码-vc++ with VHDL code, cpld accept pc serial commands, the output pwm signal to control servo motor. dual-channel, the 128. the use of extended ascii code
Platform: | Size: 959488 | Author: hxf | Hits:

[DVD] cpld_dpd

Description: DVD数字伺服系统DPD循迹伺服相位比较算法,可以根据输出波形判断循迹伺服情况-DVD Digital Servo System DPD tracking servo phase comparison algorithm, can determine the output waveform in accordance with the situation TRK
Platform: | Size: 24576 | Author: zhangli | Hits:

[Software Engineering] AB_PHASE_PWM_SOPC

Description: AB相编码器解码接口、PWM输出SOPC议案及其在运动控制卡和伺服驱动器中的应用-AB phase encoder decoder interface, PWM output SOPC motion and in motion control card and servo drive applications
Platform: | Size: 402432 | Author: 张贺 | Hits:

[VHDL-FPGA-Verilog] Thecontrolofsteppermotorandservomotorbasedonvhdl.r

Description: 本程序采用vhdl语言对步进电机及伺服电机进行控制，控制方式灵活，有变速，正反转，显示等多个模块-This procedure using VHDL language of stepper motor and servo motor control, control flexibility, have variable speed, positive, showing a number of modules, etc.
Platform: | Size: 4096 | Author: 阿汤 | Hits:

[VHDL-FPGA-Verilog] motorcontrol(vhdl)

Description: 基于FPGA的直电机伺服系统的设计的代码，VHDL语言。包括前馈控制，AD1674控制模块，ADC0809控制模块，前馈控制模块，分频模块等。-FPGA-based servo system direct the design of the electrical code, VHDL language. Including feed-forward control, AD1674 control module, ADC0809 control module, feed-forward control module, such as sub-frequency modules.
Platform: | Size: 6144 | Author: dong | Hits:

[VHDL-FPGA-Verilog] servo_module_worked

Description: verilog pwm to control servo motor on quartus
Platform: | Size: 21504 | Author: frankie | Hits:

[VHDL-FPGA-Verilog] EnDatlightversion

Description: 海德汉绝对值编码器的ENDAT2.2协议代码，用于编码器数据的解码，然后把得到的数据传送给DSP处理，我们公司用于高精度伺服驱动器上。-Heidenhain encoder absolute agreement ENDAT2.2 code encoder data for decoding the data and then transmitted to the DSP processing, our company for high-precision servo drive.
Platform: | Size: 27648 | Author: 王中超 | Hits:

[VHDL-FPGA-Verilog] DE2_PWM

Description: RC servo controller system using DE2
Platform: | Size: 1024 | Author: hazwaj | Hits:

[VHDL-FPGA-Verilog] zldj

Description: 一种直流电机伺服系统的设计，其中包括了各种控制模块的VHDL语言-A kind of DC motor servo system design, including the various control modules of VHDL language
Platform: | Size: 2002944 | Author: 刘建平 | Hits:

[VHDL-FPGA-Verilog] servo_PWM

Description: 舵机控制程序，采用VHDL编写，测试成功可同时控制多个舵机-Servo control procedures, the use of VHDL to write, test can simultaneously control multiple servo success
Platform: | Size: 1024 | Author: 郭程 | Hits:

[VHDL-FPGA-Verilog] servomat

Description: antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "servo.vhd","servo" grados DSIN 50 pwm DSOUT 100 Create output port, assign port address <name> DSIO <port_id> Create readable output port, assign port address ORG 0 Programs always start at reset vector 0 EINT If using interrupts, be sure to enable the INTERRUPT input Inicio: <<< your code here >>> load talto,0 load tbajo,0 in cantidad_a,grados-antidad_a EQU s0 talto EQU s1 Rename register sX with <name> tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant <name>, assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd", "servo.vhd","servo" grados DSIN 50 pwm DSOUT 100 Create output port, assign port address <name> DSIO <port_id> Create readable output port, assign port address ORG 0 Programs always start at reset vector 0 EINT If using interrupts, be sure to enable the INTERRUPT input Inicio: <<< your code here >>> load talto,0 load tbajo,0 in cantidad_a,grados
Platform: | Size: 1057792 | Author: Jorge | Hits:

[VHDL-FPGA-Verilog] ADC0809-control-module-code-of-VHDL

Description: 此为基于FPGA的直流电动机伺服系统的设计，具体为ADC0809控制模块的VHDL代码-This is based on FPGA for dc servo system of the design, concrete for ADC0809 control module code of VHDL
Platform: | Size: 10240 | Author: 黄平 | Hits:

[VHDL-FPGA-Verilog] AD1674-control-module-code-of-VHDL

Description: 此为基于FPGA的直流伺服系统的设计，具体为AD1674控制模块的VHDL代码-This is the dc servo system based on FPGA design, specific for AD1674 control module code of VHDL
Platform: | Size: 10240 | Author: 黄平 | Hits:

[VHDL-FPGA-Verilog] Feedback-control-module-VHDL-code

Description: 此为基于FPGA的直流伺服系统的设计，具体为反馈控制模块的VHDL代码-This is the dc servo system based on FPGA design, specific for feedback control module VHDL code
Platform: | Size: 9216 | Author: 黄平 | Hits:

[VHDL-FPGA-Verilog] Process-control-module-VHDL-code

Description: 此为基于FPGA的直流伺服系统的设计，具体为过程控制模块VHDL代码-This is the dc servo system based on FPGA design, specific for process control module VHDL code
Platform: | Size: 9216 | Author: 黄平 | Hits:

[VHDL-FPGA-Verilog] PWM-waves-generated-module-VHDL-code

Description: 此为基于FPGA的直流伺服系统的设计，具体为PWM波生成模块的VHDL代码-This is the dc servo system based on FPGA design, specific for PWM waves generated module VHDL code
Platform: | Size: 9216 | Author: 黄平 | Hits:

[Software Engineering] Radar-on-FPGA

Description: 主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。-Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given
Platform: | Size: 1137664 | Author: mabeibei | Hits:

[VHDL-FPGA-Verilog] VHDL-book3

Description: D_flipflop：1位D触发器的设计 D_fllipflop_behav：4位D触发器的设计 reg1bit：1位寄存器设计 reg4bit：4位寄存器设计 shiftreg4：一般移位寄存器的设计 ring_shiftreg4：环型移位寄存器的设计 debounce4：消抖电路的设计 clock_pulse：时钟脉冲电路的设计 count3bit_gate：3位计数器的设计 count3bit_behav：3位计数器的设计 mod5cnt：模5计数器的设计 mod10Kcnt：时钟分频器的设计 morsea：任意波生成器的设计 sw2reg：加载开关量到寄存器的设计 shift_reg8：移位数据到移位寄存器的设计 scroll：滚动7段数码显示设计 fib：Fibonacci序列设计 pwm4：PWM控制直流电机设计 pwmg：PWM控制伺服电机位置设计-D_flipflop: 1-bit D flip-flop design D_fllipflop_behav: 4-bit D flip-flop design reg1bit: 1-bit register design reg4bit: 4-bit register design shiftreg4: general shift register design ring_shiftreg4: ring shift register design debounce4: elimination shake circuit design clock_pulse: clock pulse circuit design count3bit_gate: 3-bit counter design count3bit_behav: 3-bit counter design mod5cnt: Mode 5 counter design mod10Kcnt: clock divider design morsea: arbitrary waveform generator design sw2reg: Load switch to register the design shift_reg8: shift data into the shift register design scroll: Scroll 7-segment digital display design fib: Fibonacci Sequence Design pwm4: PWM controlled DC motor design pwmg: PWM servo motor position control design
Platform: | Size: 9017344 | Author: 贾诩 | Hits:

[Other] Servo

Description: VHDL servo control from technique of Pulse Width Modulation (PWM )
Platform: | Size: 2048 | Author: Mario | Hits:

[Embeded-SCM Develop] js_fpga

Description: 使用altera的FPGA构建的sopc系统，进行嵌入式C编程，实现了伺服电机的控制。(The SOPC system is built with Altera FPGA, and embedded C programming is used to realize the servo motor control.)
Platform: | Size: 31439872 | Author: Archerlich | Hits:

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