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[Software Engineering] Virtex.files

Description: 在FPGA系统设计中，要达到性能最大化需要平衡具有混合性能效率的元器件，包括逻辑构造(fabric)、片上存储器、DSP和I/O带宽。在本文中，我将向你解释怎样能在追求更高系统级性能的过程中受益于Xilinx® 的Virtex™ -5 FPGA构建模块，特别是新的ExpressFabric™ 技术。以针对逻辑和算术功能的量化预期性能改进为例，我将探究ExpressFabric架构的主要功能。基于实际客户设计的基准将说明Virtex-5ExpressFabric技术性能平均比前一代Virtex-4 FPGA要高30％。-in FPGA system design to achieve maximum performance with the need to balance the efficiency of the mixed performance components including logical structure (fabric), on-chip memory, DSP and I / O bandwidth. In this article, I will explain how you can in the pursuit of higher system-level performance of the process to benefit from Xilinx
Platform: | Size: 97520 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] virtex-5电路原理图

Description: virtex-5电路原理图
Platform: | Size: 508682 | Author: zmzmzmzm | Hits:

[Embeded-SCM Develop] Ch2_Virtex_arch

Description: xilinx virtex architecture
Platform: | Size: 129024 | Author: flight_bai | Hits:

[Windows Develop] Ch3_fpga_design

Description: xilinx virtex fpga
Platform: | Size: 53248 | Author: flight_bai | Hits:

[Windows Develop] Ch5_Constraint

Description: xilinx virtex constraint
Platform: | Size: 494592 | Author: flight_bai | Hits:

[Embeded-SCM Develop] Ch6_Floorplanner

Description: xilinx virtex floorprint
Platform: | Size: 729088 | Author: flight_bai | Hits:

[VHDL-FPGA-Verilog] PCI_target

Description: VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
Platform: | Size: 844800 | Author: citybus | Hits:

[Documents] V4_FX_Mini_Module

Description: xilinx的嵌入式开发xps，virtex-4的mini开发板手册-Xilinx Embedded Development xps, Virtex-4 mini manual development board
Platform: | Size: 194560 | Author: 王前 | Hits:

[Documents] V4configguide

Description: xilinx的嵌入式开发xps，virtex-4的说明文档-Xilinx Embedded Development xps, Virtex-4 documentation
Platform: | Size: 595968 | Author: 王前 | Hits:

[Documents] V4ML401usersguide

Description: xilinx的嵌入式开发xps，virtex-4的401开发板用户手册-Xilinx Embedded Development xps, Virtex-4 401 development board user manual
Platform: | Size: 2046976 | Author: 王前 | Hits:

[Documents] V4ML450usersguide

Description: xilinx的嵌入式开发xps，virtex-4的450开发板用户手册-Xilinx Embedded Development xps, Virtex-4 of 450 development board user manual
Platform: | Size: 707584 | Author: 王前 | Hits:

[Documents] v4DSPusersguide

Description: xilinx的嵌入式开发xps，virtex-4的dsp发板用户手册-Xilinx Embedded Development xps, Virtex-4 dsp the board user manual
Platform: | Size: 636928 | Author: 王前 | Hits:

[Software Engineering] Virtex.files

Description: 在FPGA系统设计中，要达到性能最大化需要平衡具有混合性能效率的元器件，包括逻辑构造(fabric)、片上存储器、DSP和I/O带宽。在本文中，我将向你解释怎样能在追求更高系统级性能的过程中受益于Xilinx® 的Virtex™ -5 FPGA构建模块，特别是新的ExpressFabric™ 技术。以针对逻辑和算术功能的量化预期性能改进为例，我将探究ExpressFabric架构的主要功能。基于实际客户设计的基准将说明Virtex-5ExpressFabric技术性能平均比前一代Virtex-4 FPGA要高30％。-in FPGA system design to achieve maximum performance with the need to balance the efficiency of the mixed performance components including logical structure (fabric), on-chip memory, DSP and I/O bandwidth. In this article, I will explain how you can in the pursuit of higher system-level performance of the process to benefit from Xilinx
Platform: | Size: 97280 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] labsolutions

Description: Xilinx的培训教程的源码 virtex-Xilinx training guides source virtex
Platform: | Size: 14724096 | Author: jihuijie | Hits:

[Other] xapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集 本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。 本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input/Solution Series (ISERDES) and serial output/Solution Series (O Legacy) function.
Platform: | Size: 296960 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] Virtex-5family

Description: Virtex™ -5 系列提供 FPGA 市场中最新最强大的功能。Virtex-5 系列采用第二代 ASMBL™ （高级硅片组合模块）列式架构， 包含四种截然不同的平台（子系列），比此前任何 FPGA 系列提供的选择范围都大。每种平台都包含不同的功能配比，以满 足诸多高级逻辑设计的需求。-Virtex ™ -5 family provides the latest FPGA market, the most powerful features. Virtex-5 series using second-generation ASMBL ™ (combination of advanced silicon module) out-style architecture, contains four distinct platforms (sub-series), than any previous FPGA family offers the range of options are large. Each platform contains different functional ratio, to meet the many needs of advanced logic design.
Platform: | Size: 277504 | Author: 高超 | Hits:

[VHDL-FPGA-Verilog] Virtex-5DATASHEET(CHINESE)

Description: Virtex-5 中文版数据手册，找了好久才找到的。与大家分享。-Chinese version of Virtex-5 data sheet, looking for a long time to find. To share with you.
Platform: | Size: 4423680 | Author: 郭暧闵 | Hits:

[VHDL-FPGA-Verilog] Virtex-5_FPGA_yonghuzhinan

Description: Virtex-5_FPGA_用户指南，中文版，详细讲解了Virtex-5_FPGA各个功能-Virtex-5_FPGA_ User' s Guide, the Chinese version of the Virtex-5_FPGA explain in detail the various functional
Platform: | Size: 5242880 | Author: 木一 | Hits:

[Embeded-SCM Develop] Virtex-5EMAC

Description: This application note describes a system using the Virtex™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded Tri-Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board, and a PC-based Graphical User Interface (GUI) to control the demonstration platform.-This application note describes a system using the Virtex ™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded Tri- Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board, and a PC-based Graphical User Interface (GUI) to control the demonstration platform.
Platform: | Size: 492544 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] Virtex-5-FPGA_DDR2_SDRAM_data

Description: Virtex-5 FPGA实现的高性能 DDR2 SDRAM数据采集，需要对V5有一定基础的人学习-Virtex-5 FPGA DDR2 SDRAM to achieve high-performance data acquisition, the need for V5 have to learn some basic
Platform: | Size: 436224 | Author: apple_rao | Hits:
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