Search - Viterbi VHDL

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[VHDL-FPGA-Verilog] Convolutional encoding and Viterbi decoding with k DL : 0: 卷积码编码和维特比解码当K为7 时供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Update : 2025-02-17 Size : 248kb Publisher : 周小川
[Other Embeded program] SKRETD(low_power) DL : 0: 硕士论文，viterbi译码器的低功耗设计，最后附带源码，VHDL-master's thesis, Viterbi Decoder low-power design, the final collateral source, VHDL
Update : 2025-02-17 Size : 372kb Publisher : xialu
[Communication-Mobile] turbo_VHDL DL : 0: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
Update : 2025-02-17 Size : 151kb Publisher :
[Program doc] Viterbi DL : 0: 三篇关于Viterbi FPGA编译码器的优化设计文档： 1、Viterbi译码器的FPGA设计实现与优化.pdf 2、Viterbi译码器的低功耗设计.pdf 3、基于FPGA的高速并行Viterbi译码器的设计与实现.pdf-3 on the Viterbi FPGA optimization codecs design documents: 1, Viterbi decoder FPGA Design Implementation and Optimization. Pdf2, Viterbi decoder, low-power design. Pdf3, high-speed FPGA-based parallel Viterbi decoder Design and Implementation. pdf
Update : 2025-02-17 Size : 441kb Publisher : helei_zju
[VHDL-FPGA-Verilog] viterbi DL : 0: VHDL 程序，实现vertibe的编码和解码。-VHDL procedures vertibe realize the encoding and decoding.
Update : 2025-02-17 Size : 2kb Publisher : 左麟
[VHDL-FPGA-Verilog] viterbi DL : 0: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Update : 2025-02-17 Size : 61kb Publisher : yaoyongshi
[Software Engineering] viterbi DL : 0: 适合高速Viterbi译码器的hdl的设计与实现-脢脢潞脧赂脽脣脵Viterbi脪毛脗毛脝梅渭脛hdl渭脛脡猫录脝脫毛脢渭脧脰
Update : 2025-02-17 Size : 433kb Publisher : mediative
[Program doc] viterbi DL : 0: 基于XilinxFPGA的高速Viterbi回溯译码器-Based on retrospective XilinxFPGA high-speed Viterbi decoder
Update : 2025-02-17 Size : 194kb Publisher : mediative
[Program doc] viterbi DL : 0: 高速Viterbi处理器的并行算法和结构-High-speed Viterbi processor parallel algorithm and structure
Update : 2025-02-17 Size : 245kb Publisher : mediative
[VHDL-FPGA-Verilog] viterbi DL : 0: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Update : 2025-02-17 Size : 250kb Publisher : mediative
[Program doc] viterbi DL : 0: 维特比译码器的asic设计的相关论文-Viterbi Decoder asic design related articles
Update : 2025-02-17 Size : 271kb Publisher : mediative
[VHDL-FPGA-Verilog] Viterbi DL : 0: Viterbi译码器的FPGA实现代码,来在国外大学论坛.-Viterbi decoder implementation of the FPGA code to the Forum at foreign universities.
Update : 2025-02-17 Size : 8kb Publisher : 蔡敏
[VHDL-FPGA-Verilog] viterbi DL : 0: 这是一个用VERILOG HDL语言编写的viterbi译码程序-This is a language VERILOG HDL by the viterbi decoding process
Update : 2025-02-17 Size : 2kb Publisher : chenxiaoming
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Update : 2025-02-17 Size : 3kb Publisher : xiongherui
[VHDL-FPGA-Verilog] viterbi DL : 0: viterbi decoder with convolutional encoder
Update : 2025-02-17 Size : 1.33mb Publisher : phani
[VHDL-FPGA-Verilog] viterbi DL : 0: verilog code for viterbi encoder and decoder
Update : 2025-02-17 Size : 13kb Publisher : kamran
[VHDL-FPGA-Verilog] Viterbi DL : 0: 实现VHDL的维特比译码 -VHDL Viterbi decoding to achieveVHDL Viterbi decoding to achieve
Update : 2025-02-17 Size : 145kb Publisher : 飞熊
[Internet-Network] viterbi-3.0.1 DL : 0: 前向纠错viterbi-3.0.1的实现测试通过-FEC viterbi-3.0.1 implementation tested
Update : 2025-02-17 Size : 23kb Publisher : chack
[VHDL-FPGA-Verilog] viterbi DL : 0: This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.-This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.
Update : 2025-02-17 Size : 639kb Publisher : Nagendran
[VHDL-FPGA-Verilog] viterbi DL : 0: 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Update : 2025-02-17 Size : 90kb Publisher : Fengxiaodong

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