Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - XILINX RAM

Search list

[Other resource] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \\ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19762 | Author: 朱效志 | Hits:

[Other resource] FCRAM_controller__xilinx

Description: 开发环境ise6+，fcram快速循环ram,这个市控制器源代码，xilinx提供
Platform: | Size: 50137 | Author: 邱劲松 | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
Platform: | Size: 54272 | Author: 刘汉忠 | Hits:

[VHDL-FPGA-Verilog] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 615424 | Author: ruan | Hits:

[VHDL-FPGA-Verilog] my_fifo_vhdl

Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
Platform: | Size: 19456 | Author: 朱效志 | Hits:

[Embeded-SCM Develop] xilinx

Description: xilinx 开发板原理图,里面含有pcb图,自己完全可以做一块来玩,不用买别人的,很省钱,又锻炼了自己.-Xilinx development board schematic diagram, which contains pcb chart their own can make a play, do not buy someone else
Platform: | Size: 305152 | Author: 萧勇 | Hits:

[VHDL-FPGA-Verilog] dualporttst-1_0

Description: xilinx 开发板原程序，双口RAM控制-Xilinx development board the original procedures, dual-port RAM control
Platform: | Size: 195584 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 用双端口ram实现异步fifo，采用格雷码，避免产生毛刺。-Using dual-port ram realize asynchronous fifo, the use of Gray code, avoiding the production of burr.
Platform: | Size: 1024 | Author: shili | Hits:

[VHDL-FPGA-Verilog] BlockRAM

Description: xilinx BlockRAM 级联，利用Xilinx原语（非IP Core），更大灵活性-xilinx BlockRAM cascade, using Xilinx primitive (non-IP Core), greater flexibility
Platform: | Size: 2048 | Author: blackmew | Hits:

[Other] my_ram_vhdl

Description: how to infer ram for fpga altera xilinx
Platform: | Size: 1024 | Author: yusuf.abdullah | Hits:

[VHDL-FPGA-Verilog] RAM

Description: 用VHDL编写一个字长16位，容量128B的RAM控制实现程序，并进行设计综合和功能模拟 。含源程序，及实验要求。适合初学者学习使用。-VHDL prepared with a 16-bit word length, 128B of the RAM capacity to achieve process control and design of analog integrated and functional. Containing source code, and experimental requirements. Suitable for beginners learning to use.
Platform: | Size: 9216 | Author: 赵剑平 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[VHDL-FPGA-Verilog] TechXclusives-ReconfiguringBlockRAMs

Description: Xilinx FPGA block RAM reconfig via JTAG
Platform: | Size: 104448 | Author: Kraja | Hits:

[VHDL-FPGA-Verilog] TechXclusives-UsingLeftoverMultipliersandBlockRAM

Description: Xilinx FPGA using leftover multipliers and block RAM
Platform: | Size: 62464 | Author: Kraja | Hits:

[VHDL-FPGA-Verilog] dpRam1

Description: Dual port ram design project developed in Xilinx using VHDL
Platform: | Size: 741376 | Author: qaziguy | Hits:

[VHDL-FPGA-Verilog] blk_write

Description: verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
Platform: | Size: 2048 | Author: y_gt | Hits:

[VHDL-FPGA-Verilog] FPGA-Prototyping-by-VHDL-Examples---Xilinx-Sparta

Description: FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others-FPGA prototyping by VHDL examples include FIFO,RAM,ROM,filters, registers and others
Platform: | Size: 16619520 | Author: Aleks | Hits:

[VHDL-FPGA-Verilog] mypro_synfifo

Description: 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
Platform: | Size: 1275904 | Author: Hurley | Hits:

[VHDL-FPGA-Verilog] dpram

Description: FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
Platform: | Size: 352256 | Author: hzh | Hits:

[VHDL-FPGA-Verilog] pg058-blk-mem-gen

Description: blockram的手册，适合开发者使用是xilinx的(Blockram manual, suitable for developers to use, is Xilinx)
Platform: | Size: 1636352 | Author: CrazyICer | Hits:
« 12 3 »

CodeBus www.codebus.net