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[VHDL-FPGA-Verilog] S3Demo

Description: 用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
Platform: | Size: 291840 | Author: 计算机 | Hits:

[Software Engineering] ise_tutarial

Description: xilinx培训教程讲义，好几个ppt，讲解十分详细-xilinx Training Guide overhead, several ppt, on the very detailed
Platform: | Size: 12367872 | Author: jihuijie | Hits:

[Technology Management] 06529_xilinx

Description: XILINX的时序约束教程，详细的介绍了各种时序关系和约束-Timing Constraints Guide, a detailed introduction to the various temporal relations and constraints
Platform: | Size: 1258496 | Author: fei0318 | Hits:

[Documents] ise

Description: xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能-Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance
Platform: | Size: 271360 | Author: 江巧微 | Hits:

[Software Engineering] VHDL

Description: 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。-The system design using VHDL language, using top-down design method. Selection of the target device Xilinx
Platform: | Size: 297984 | Author: 西西 | Hits:

[Windows Develop] parallel_spi_programmer1p65

Description: 该程序的功能为通过计算机并口模拟SPI时序，时序将计算机上二进制文件的数据写入到Atmel spi flash中去。 下载时使用的下载线为Xilinx公司的parallel III标准下载线； 软件支持usb下载，不够下载线是本人自己做的； 下载时，可以指定将数据写入到那一段地址，长度是多少，可以回读数据； 代码使用MFC,有多线程操作，SDI，使用winio作为底层操作 该程序为本人自己的作品。调试通过，下载速率200kbps左右。-The functions of the program through the computer parallel port SPI timing simulation, timing will be computer binary file data written to the Atmel spi flash go. Download download cable for use Xilinx
Platform: | Size: 2718720 | Author: 张计恒 | Hits:

[VHDL-FPGA-Verilog] ISE_assistant_design_tool

Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
Platform: | Size: 1589248 | Author: joan | Hits:

[VHDL-FPGA-Verilog] PPT_timing-constraint

Description: PPT的形式演示Xilinx-ISE环境下时序约束的实现个结果
Platform: | Size: 615424 | Author: joan | Hits:

[VHDL-FPGA-Verilog] CPLDexperiment

Description: 本实验教程选用Xilinx公司的产品X9572，与之配套的开发软件为ISE4.1i，可进行原理图的输入和VHDL硬件描述语言的输入，并且可利用Modelsim进行功能仿真和时序仿真。-In this study, selected Xilinx tutorial products X9572, with supporting the development of software for ISE4.1i, schematic can be input and VHDL hardware description language input, and can use Modelsim functional simulation and timing simulation.
Platform: | Size: 584704 | Author: bin | Hits:

[Other] Huawei_FPGA_Design_Senior_Skills_and_Tips_for_Xili

Description: 华为 FPGA 设计高级技巧 Xilinx 篇， 涉及 FPGA 综合、时序优化、编码风格 -Huawei skills Xilinx Advanced FPGA Design articles, involving FPGA synthesis, timing optimization, coding style
Platform: | Size: 1705984 | Author: | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: Xilinx时序约束培训教材,对于时序仿真有很好的指导意义-Training materials Xilinx timing constraints, timing simulation for a very good guide
Platform: | Size: 687104 | Author: zhangchen | Hits:

[VHDL-FPGA-Verilog] tlc3548VHDL

Description: VHDL实现对TLC3548时序的控制 FPGA控制具有时序简单,速率快等优点-VHDL COUNTER TLC3548
Platform: | Size: 627712 | Author: 赵惠军 | Hits:

[VHDL-FPGA-Verilog] TimingConstraint

Description: xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material
Platform: | Size: 1339392 | Author: juan | Hits:

[Embeded-SCM Develop] Xilin

Description: Xilinx时序约束培训教材,主要介绍FPGA的时序约束。-Xilinx
Platform: | Size: 1258496 | Author: nick | Hits:

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

Description: xilinx公司原版的DDR时序控制源码.-xilinx' s original source code of the DDR timing control.
Platform: | Size: 680960 | Author: suyufeng | Hits:

[VHDL-FPGA-Verilog] Xilinx-fpga

Description: xilinx时序约束的重要官方资料。非常有用-Xilinx timing constraints of important official material.
Platform: | Size: 296960 | Author: 小王 | Hits:

[VHDL-FPGA-Verilog] Xilinx-constraints-guide2

Description: xilinx时序约束指南，详细的说明和使用操作实例-xilinx timing constraints
Platform: | Size: 1257472 | Author: zhongyali | Hits:

[VHDL-FPGA-Verilog] Xilinx-design-timing-constraints

Description: 很有用的Xilinx时序约束设计资料，很适合初学者-Very useful Xilinx timing constraints, design data, is very suitable for beginners
Platform: | Size: 1251328 | Author: 李静 | Hits:

[Books] Xilinx时序约束培训教材

Description: Xilinx时序约束培训教材，教你怎样设计时序收敛的FPGA程序。
Platform: | Size: 1259912 | Author: gxb2525775 | Hits:

[Documents] 时序分析

Description: XILINX 时序约束使用指南笔记 ——时序约束介绍 时序约束方法 时序约束原则等(XILINX time series constraints use guide notes -- time series constraints introducing time series constraint principles, etc.)
Platform: | Size: 1348608 | Author: 李天 | Hits:
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