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[Patch] ISE12.4 lic

Description: ISE 12.4 license文件
Platform: | Size: 5316 | Author: analog2k4@126.com | Hits:

[VHDL-FPGA-Verilog] ISE_chinese_user_guide

Description: Xilinx—ISE的中文使用说明，写的很简单，但对于入门者很实用。看过市面上很多Xilinx的书，发现很多都是在这本书的基础上稍加改写，。
Platform: | Size: 915456 | Author: joan | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[Linux-Unix] mgc_licen(1)

Description: license for ise12.2,最新而且很好用，请放心使用。-license for ise12.2，It s lastest fot ise 12.2,good ease to ues.
Platform: | Size: 387072 | Author: 邵磊 | Hits:

[VHDL-FPGA-Verilog] ADPCMDecoder

Description: ADPCM decoder working on Xilinx ISE 12.2 code includes core ICON ILA VIO test on chipscope
Platform: | Size: 2048 | Author: DANIEL PAN | Hits:

[VHDL-FPGA-Verilog] xilinx_ise_12

Description: 最新xilinx_ISE-12.3 version License 扩展名.lic-xilinx_ISE-12.3 version License
Platform: | Size: 5120 | Author: TBR | Hits:

[VHDL-FPGA-Verilog] XilinxISEDesignSuite12.1

Description: Xilinx ISE Design Suite 12.1 cd key
Platform: | Size: 1024 | Author: grs | Hits:

[SCM] XILINX-ISE-MODELSIN-SE-Simulation

Description: Modelsim 10.0a 中建立 Xilinx ISE 13.1的仿真库及其之间调用设置详解。-Modelsim 10.0a create Xilinx 13.1 calls between the simulation library and its setting Detailed.
Platform: | Size: 478208 | Author: 迷失De信仰 | Hits:

[VHDL-FPGA-Verilog] xilinx_EDK_lesson_ISE12

Description: Xilinx EDK 系統設計教學 使用ISE 12-Xilinx EDK lesson step by step for ISE 12
Platform: | Size: 13309952 | Author: osabado | Hits:

[Embeded Linux] Xilinx

Description: Xilinx12.3和12.4 license 加强版支持更多ipcore 以及modelsim编译ise 库的方法说明-Xilinx12.3 and 12.4 license as well as enhanced support for more ipcore modelsim compile ise description of the ways library
Platform: | Size: 1235968 | Author: 王垚 | Hits:

[VHDL-FPGA-Verilog] ygyTest

Description: 利用开源网站上的8051核，在Spartan 3A开发板上实现成功，开发环境是Xilinx ISE Design Suite 12.3，顶层文件基于原理图开发，扩展了外部ROM和RAM，且更改了地址宽度-implment the mc8051 IP in spartan-3A FPGA starten kit.
Platform: | Size: 18179072 | Author: 杜春城 | Hits:

[source in ebook] counter_12

Description: 12进制计数器工程，用xilinx ISE设计，供初学者学习-12 hex counter project using xilinx the ISE design for beginners to learn
Platform: | Size: 112640 | Author: 皇天 | Hits:

[Software Engineering] an-FPGA-example-base-Xilinx-ISE-12.4

Description: 基于ISE 12.4的FPGA设计基本流程, 熟悉赛灵思 ISE 12.4 的最佳快速入门-an FPGA example base Xilinx-ISE-12.4
Platform: | Size: 578560 | Author: panqihe | Hits:

[VHDL-FPGA-Verilog] VIRTEX2-ISE-VHDL

Description: XILINX virtex5 板子上做演化硬件时ISE 12.1中的硬件构架语言描述-XILINX virtex5 VHDL
Platform: | Size: 1024 | Author: 陈芹芹 | Hits:

[VHDL-FPGA-Verilog] Lab3_mux24a

Description: 4位2选1多路选择器的设计与实现。nexy3开发板。本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3.
Platform: | Size: 100352 | Author: penglx1803 | Hits:

[VHDL-FPGA-Verilog] Lab4_hex7seg

Description: 7段译码器的设计与实现.nexy3开发板。通过使用ISE软件进行7段译码器的设计与实现。-Xilinx ISE 12.3.nexy3
Platform: | Size: 161792 | Author: penglx1803 | Hits:

[VHDL-FPGA-Verilog] Lab5_x7seg

Description: 7段显示管的设计与实现.nexy3开发板。在2个7段显示管上显示一个2位的十六进制数，本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3.
Platform: | Size: 223232 | Author: penglx1803 | Hits:

[VHDL-FPGA-Verilog] Lab6_decode38a

Description: 3-8译码器的设计与实现.3-8译码器的真值表，本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3
Platform: | Size: 105472 | Author: penglx1803 | Hits:

[Program doc] Modelsim-Xilinx--ISE

Description: Modelsim编译Xilinx ISE 12.3库，详细教程，很好用的，适合初学者-Modelsim compiled Xilinx ISE 12.3 Library, a detailed tutorial, very easy to use for beginners
Platform: | Size: 1227776 | Author: 吕攀攀 | Hits:

[Special Effects] 15010120041_高瑞雪_lab2

Description: 在本实验中，将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC（Multiplier Accumulator），并使用System Generator 的Resource Estimator块来估计资源利用率。 在仿真Simulink中的设计之后，将从该设计中生成VHDL代码和内核，并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specified MAC - based bandpass filter using the basic block of the system generator)
Platform: | Size: 800768 | Author: 瑞雪儿 | Hits:

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