Search - Xilinx ISE 8.1

[Other resource] bujindianjiVHDL

Description: 步进电机定位控制系统VHDL程序与仿真波形．已经在xilinx ISE 8.1上验证．完全正确．-positioning stepper motor control system procedures and VHDL simulation waveform. Xilinx ISE has tested 8.1. Absolutely correct.
Platform: | Size: 4965 | Author: 罗辉 | Hits:

[VHDL-FPGA-Verilog] sampleVHDL

Description: 采样等精度测量的VHDL程序．．在xilinx ISE 8.1上验证通过-sampling and other precision measurement of VHDL program. . In xilinx ISE tested through 8.1.
Platform: | Size: 122880 | Author: 罗辉 | Hits:

[Software Engineering] xilinx_ise_edk8.1_register

Description: xilinx ise edk8.1注册器-xilinx ise edk8.1 for registration
Platform: | Size: 65536 | Author: 张菊兰 | Hits:

[Other Embeded program] xup_v2pro

Description: Xilinx ISE&EDK 8.2平台的快速点餐系统设计-Xilinx ISE
Platform: | Size: 993280 | Author: huosijia | Hits:

[Other Embeded program] Face_Detect

Description: Xilinx ISE&EDK 8.2平台的人脸检测系统设计-Xilinx ISE
Platform: | Size: 284672 | Author: huosijia | Hits:

[File Format] ise_keygen

Description: to generate keygen for xilinx ise edk 8.1 9.1 9.2
Platform: | Size: 66560 | Author: malik | Hits:

[VHDL-FPGA-Verilog] 45561564

Description: 典型实例10.8 字符LCD接口的设计与实现软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 1. 本实例控制开发板上面的LCD的显示； 2. 工程在\project文件夹里面 3. 源文件和管脚分配在\rtl文件夹里面 4. 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Typical examples of character LCD interface 10.8 The Design and Implementation of Software Development Environment: ISE 7.1i development environment hardware: Hurricane II on behalf of the red-Xilinx Edition 1. The above examples of the control board of the LCD display 2. Projects \ project folder inside 3. the distribution of the source file and pin in \ rtl folder inside 4. download files in \ download folder inside,. mcs file for the PROM mode download,. bit for the JTAG debugger to download the file.
Platform: | Size: 313344 | Author: 王磊 | Hits:

[VHDL-FPGA-Verilog] ADC0832_test

Description: ADC0832是一个8-bit的ADC转化芯片，工作频率为250Khz，最大频率可达400Khz，转化通道有两个，输入电压可分有单端或差分形式。本测试使用单端电压输入形式，从昔年的CH0输入电压，使用Xilinx XC3S200AN开发板，并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证，输入电压范围是0V--5.5V,当电压达到5.5V时，满刻度.-ADC0832 is an 8-bit conversion of the ADC chip, the working frequency of 250Khz, the maximum frequency of up to 400Khz, into two channels, the input voltage can be divided into single-ended or differential form. This test used the form of single-ended voltage input, from the previous years of the CH0 input voltage, the use of Xilinx XC3S200AN development board, Xilinx ise tools and use of ChipScope tool to see into the post-DO data is correct. Validated, input voltage range is 0V- 5.5V, when the voltage reaches 5.5V, the full-scale.
Platform: | Size: 3628032 | Author: zhangjiansen | Hits:

[VHDL-FPGA-Verilog] XilinxISE8

Description: This tutorial gives a description of the features and additions to Xilinx® ISE™ 8.2i. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools. This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge. You may choose to follow one of three tutorial flows available in this document. For information about the tutorial flows, see “Tutorial Flows.”-This tutorial gives a description of the features and additions to Xilinx® ISE™ 8.2i. The primary focus of this tutorial is to show the relationship among the design entry tools, Xilinx and third-party tools, and the design implementation tools. This guide is a learning tool for designers who are unfamiliar with the features of the ISE software or those wanting to refresh their skills and knowledge. You may choose to follow one of three tutorial flows available in this document. For information about the tutorial flows, see “Tutorial Flows.”
Platform: | Size: 1563648 | Author: JERRY | Hits:

[VHDL-FPGA-Verilog] License

Description: Xilinx ISE 8.2i的license-Xilinx ISE 8.2i s license
Platform: | Size: 3072 | Author: 张琼 | Hits:

[Documents] dividefreq

Description: Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
Platform: | Size: 538624 | Author: xanflixus | Hits:

[VHDL-FPGA-Verilog] Leds

Description: Multiple frequency dividers in VHDL, with comments in Spanish. Is a project done with Xilinx ISE application. It divides 50 MHz in 1, 2, 4 and 8 Hz.
Platform: | Size: 372736 | Author: xanflixus | Hits:

[Books] Block_Memory_Generator_v3.3

Description: Xilinx IP core 生成手册-Block_Memory_Generator
Platform: | Size: 1935360 | Author: wang pu | Hits:

[Other] dbox2-ide

Description: Die Dateien sind die Sourcen um die Firmware des IDE-CPLD zu generieren. Project-Files für die Xilinx-Software habe ich nicht gespeichert, da diese leicht neu generiert werden kö nnen. Zuletzt habe ich die Version ISE 8.2 verwendet, aber die neueren werden wahrscheinlich ä hnlich funktionieren: Starte die Xilinx Software und beginne ein neues Project mit dem Project-Wizard: Device: XC95144XL Package: TQ144 (TQ100 auf den Hallenbergs Boards) Speed: -5 (oder was auch immer ihr habt, steht auf dem Chip)-Die Dateien sind die Sourcen um die Firmware des IDE-CPLD zu generieren. Project-Files für die Xilinx-Software habe ich nicht gespeichert, da diese leicht neu generiert werden kö nnen. Zuletzt habe ich die Version ISE 8.2 verwendet, aber die neueren werden wahrscheinlich ä hnlich funktionieren: Starte die Xilinx Software und beginne ein neues Project mit dem Project-Wizard: Device: XC95144XL Package: TQ144 (TQ100 auf den Hallenbergs Boards) Speed: -5 (oder was auch immer ihr habt, steht auf dem Chip)
Platform: | Size: 93184 | Author: mario | Hits:

[SCM] adfmreceiver

Description: The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked. Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal. The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device.
Platform: | Size: 658432 | Author: vijay | Hits:

[VHDL-FPGA-Verilog] proj1

Description: 在Xilinx的ISE下用VHDL实现的3-8线译码器。-In the Xilinx ISE implementation using VHDL 3-8 line decoder.
Platform: | Size: 154624 | Author: 张航 | Hits:

[Other] yimaqi_beh

Description: 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description types, i.e., behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.
Platform: | Size: 1024 | Author: maria | Hits:

[VHDL-FPGA-Verilog] my_uart2

Description: 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Summary ---------------- INFO:WebTalk:1- WebTalk is enabled because you are using a WebPACK license. INFO:WebTalk:8- WebTalk Install setting is ON. INFO:WebTalk:6- WebTalk User setting is ON. INFO:WebTalk:5- D:/Xilinxsheji/my_uart2/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at D:/xilinx13.2/ISE_DS/ISE/data/reports/webtalk_introduction.html
Platform: | Size: 253952 | Author: chen | Hits:

[Special Effects] 15010120041_高瑞雪_lab2

Description: 在本实验中，将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC（Multiplier Accumulator），并使用System Generator 的Resource Estimator块来估计资源利用率。在仿真Simulink中的设计之后，将从该设计中生成VHDL代码和内核，并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specified MAC - based bandpass filter using the basic block of the system generator)
Platform: | Size: 800768 | Author: 瑞雪儿 | Hits:

[VHDL-FPGA-Verilog] 3-8译码器VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4；利用XIlinX编程，使用VHDL语言来描述组合逻辑器件3-8译码器(In the FPGA:Spartan-3E development board series, XC3S500E, FGT320, -4 package: speed; the use of XIlinX programming, using VHDL language to describe the combination of the 3-8 decoder logic device)
Platform: | Size: 10240 | Author: lixilin | Hits:

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