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[Other resource] HDL编码风格与编码指南大家看看啊

Description: 大家好没办法还是那句话我现在用maxplus2有高手跟我联系请上qq94229631 手机13788910703上海的我姓曹-everyone no way I reiterate I will maxplus2 with a master please contact me on the phone 13788910703 qq94229631 I Shanghai surnamed Cao
Platform: | Size: 6209 | Author: 曹延安 | Hits:

[Other resource] Verilog HDL设计练习进阶

Description: 初学verilog HDL时找的好资料大家共享-Beginners should try to find a good share information
Platform: | Size: 681405 | Author: chencsw | Hits:

[Develop Tools] A Verilog HDL Test Bench Primer

Description: Lattice公司的A Verilog HDL Test Bench Primer应用手册-Lattice A Verilog HDL Test Bench Primer Handbook
Platform: | Size: 58083 | Author: 陈正一 | Hits:

[WEB Code] HDL

Description: HDL 编码风格与编码指导,介绍了详细的vhdl和verilog hdl语言的编程风格-HDL coding style and coding guidance, presented a detailed VHDL and Verilog HDL language programming style
Platform: | Size: 63659 | Author: xwca | Hits:

[Other resource] Verilog-HDL

Description: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
Platform: | Size: 784543 | Author: 东子 | Hits:

[Other] HDL CHIP DESIGN

Description: A practical guide for designing ,synthesizing and simulating ASICs and FPGA using VHDL and verilog hdl
Platform: | Size: 1472502 | Author: zxj0903 | Hits:

[Embeded-SCM Develop] verilog实例 [43项]

Description: 嵌入式可编程器件CPLD的典型实例压缩包，共计43个源码文件。使用ALTERA的 Muxplus 软件即可编辑仿真相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software available from the Education Network ftp download [days Web inquiries, many sites provide]
Platform: | Size: 181248 | Author: 吴旭辉 | Hits:

[Windows Develop] 有译zhup

Description: 交通灯控制电路一、设计任务与要求 1．设计一个十字路口的交通灯控制电路，要求甲车道和乙车道两条交叉道路上的车辆交替运行，每次通行时间都设为25秒； 2．要求黄灯先亮5秒，才能变换运行车道； 3．黄灯亮时，要求每秒钟闪亮一次。二、实验预习要求 1．复习数字系统设计基础。 2．复习多路数据选择器、二进制同步计数器的工作原理。 3．根据交通灯控制系统框图，画出完整的电路图。-a control circuit design tasks and requirements 1. Design a crossroads of traffic lights control circuit, and requested a B lane cross-road of two lanes of traffic on the turn of operation, each time prevailing Set 25 seconds; 2. Asked yellow first-five seconds, can transform running lanes; 3. Bright yellow light, flashing a request per second. Two experimental rehearsal requirements 1. Review of digital systems design basis. 2. Review of Multiple Choice of data, binary synchronous counter to the principle. 3. According to the traffic light control system block diagram to depict the integrity of the circuit.
Platform: | Size: 1024 | Author: 刘鹏 | Hits:

[ARM-PowerPC-ColdFire-MIPS] ethernet_verilog

Description: 这是一个很好的Verilog 编写的8位RISC CPU源码（可做为MCU），并且包括完整的C 语言的测试代码。-This is a very good preparation Verilog 8-bit RISC CPU source (available as MCU), and includes a complete C language test code.
Platform: | Size: 78848 | Author: 张念华 | Hits:

[VHDL-FPGA-Verilog] 数字频率计实验报告

Description: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下：测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形：方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Platform: | Size: 144384 | Author: 兰 | Hits:

[VHDL-FPGA-Verilog] Verilog HDL设计练习进阶

Description: 初学verilog HDL时找的好资料大家共享-Beginners should try to find a good share information
Platform: | Size: 680960 | Author: chencsw | Hits:

[Books] A Verilog HDL Test Bench Primer

Description: Lattice公司的A Verilog HDL Test Bench Primer应用手册-Lattice A Verilog HDL Test Bench Primer Handbook
Platform: | Size: 57344 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
Platform: | Size: 784384 | Author: 东子 | Hits:

[Other] Verilog-HDL

Description: 本书从实际的角度介绍了硬件描述语言Verilog-HDL。通过动手实践体验其语法结构、功能等内涵-This book from a practical point of introduction of hardware description language Verilog-HDL. By doing practical experience of its grammatical structure and function of the connotation of
Platform: | Size: 5829632 | Author: 皱接 | Hits:

[VHDL-FPGA-Verilog] verilog-hdl

Description: verilog—hdl教程135例大量的数字点电路例子-verilog-hdl Tutorial 135 cases of a large number of digital point circuit example
Platform: | Size: 168960 | Author: awake | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 《Verilog-HDL实践与应用系统设计》一书中的光盘源文件- Verilog-HDL practice and application of system design, a book on CD-ROM source file
Platform: | Size: 771072 | Author: 范田田 | Hits:

[VHDL-FPGA-Verilog] caiyang

Description: 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory contains A/D sampling control circuit design method, and gives the A/D sampling control circuit of the V HDL source code and the sample stored in the top-level circuit schematic.
Platform: | Size: 338944 | Author: 于银 | Hits:

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[Other resource] HDL编码风格与编码指南大家看看啊

[Other resource] Verilog HDL设计练习进阶

[Develop Tools] A Verilog HDL Test Bench Primer

[WEB Code] HDL

[Other resource] Verilog-HDL

[Other] HDL CHIP DESIGN

[Embeded-SCM Develop] verilog实例 [43项]

[Windows Develop] 有译zhup

[ARM-PowerPC-ColdFire-MIPS] ethernet_verilog

[VHDL-FPGA-Verilog] 数字频率计实验报告

[VHDL-FPGA-Verilog] Verilog HDL设计练习进阶

[Books] A Verilog HDL Test Bench Primer

[VHDL-FPGA-Verilog] Verilog-HDL

[Other] Verilog-HDL

[VHDL-FPGA-Verilog] verilog-hdl

[VHDL-FPGA-Verilog] Verilog-HDL

[VHDL-FPGA-Verilog] caiyang

[VHDL-FPGA-Verilog] Verilog-HDL

[VHDL-FPGA-Verilog] X-HDL

[VHDL-FPGA-Verilog] A-Verilog-HDL-Primer

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